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arch
mips
math-emu
sp_flong.c
Go to the documentation of this file.
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/* IEEE754 floating point arithmetic
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* single precision
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*/
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/*
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* MIPS floating point support
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* Copyright (C) 1994-2000 Algorithmics Ltd.
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*/
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#include "
ieee754sp.h
"
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ieee754sp
ieee754sp_flong
(
s64
x
)
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{
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u64
xm;
/* <--- need 64-bit mantissa temp */
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int
xe
;
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int
xs
;
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CLEARCX
;
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if
(x == 0)
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return
ieee754sp_zero
(0);
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if
(x == 1 || x == -1)
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return
ieee754sp_one
(x < 0);
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if
(x == 10 || x == -10)
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return
ieee754sp_ten
(x < 0);
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xs = (x < 0);
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if
(xs) {
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if
(x == (1ULL << 63))
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xm = (1ULL << 63);
/* max neg can't be safely negated */
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else
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xm = -
x
;
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}
else
{
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xm =
x
;
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}
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xe =
SP_MBITS
+ 3;
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if
(xm >> (
SP_MBITS
+ 1 + 3)) {
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/* shunt out overflow bits
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*/
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while
(xm >> (
SP_MBITS
+ 1 + 3)) {
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SPXSRSX1
();
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}
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}
else
{
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/* normalize in grs extended single precision */
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while
((xm >> (
SP_MBITS
+ 3)) == 0) {
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xm <<= 1;
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xe--;
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}
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}
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SPNORMRET1
(xs, xe, xm,
"sp_flong"
, x);
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}
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ieee754sp
ieee754sp_fulong
(
u64
u
)
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{
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if
((
s64
) u < 0)
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return
ieee754sp_add
(
ieee754sp_1e63
(),
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ieee754sp_flong
(u & ~(1ULL << 63)));
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return
ieee754sp_flong
(u);
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}
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