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spear1340_clock.c
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1 /*
2  * arch/arm/mach-spear13xx/spear1340_clock.c
3  *
4  * SPEAr1340 machine clock framework source file
5  *
6  * Copyright (C) 2012 ST Microelectronics
7  * Viresh Kumar <[email protected]>
8  *
9  * This file is licensed under the terms of the GNU General Public
10  * License version 2. This program is licensed "as is" without any
11  * warranty of any kind, whether express or implied.
12  */
13 
14 #include <linux/clk.h>
15 #include <linux/clkdev.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/of_platform.h>
19 #include <linux/spinlock_types.h>
20 #include <mach/spear.h>
21 #include "clk.h"
22 
23 /* Clock Configuration Registers */
24 #define SPEAR1340_SYS_CLK_CTRL (VA_MISC_BASE + 0x200)
25  #define SPEAR1340_HCLK_SRC_SEL_SHIFT 27
26  #define SPEAR1340_HCLK_SRC_SEL_MASK 1
27  #define SPEAR1340_SCLK_SRC_SEL_SHIFT 23
28  #define SPEAR1340_SCLK_SRC_SEL_MASK 3
29 
30 /* PLL related registers and bit values */
31 #define SPEAR1340_PLL_CFG (VA_MISC_BASE + 0x210)
32  /* PLL_CFG bit values */
33  #define SPEAR1340_CLCD_SYNT_CLK_MASK 1
34  #define SPEAR1340_CLCD_SYNT_CLK_SHIFT 31
35  #define SPEAR1340_GEN_SYNT2_3_CLK_SHIFT 29
36  #define SPEAR1340_GEN_SYNT_CLK_MASK 2
37  #define SPEAR1340_GEN_SYNT0_1_CLK_SHIFT 27
38  #define SPEAR1340_PLL_CLK_MASK 2
39  #define SPEAR1340_PLL3_CLK_SHIFT 24
40  #define SPEAR1340_PLL2_CLK_SHIFT 22
41  #define SPEAR1340_PLL1_CLK_SHIFT 20
42 
43 #define SPEAR1340_PLL1_CTR (VA_MISC_BASE + 0x214)
44 #define SPEAR1340_PLL1_FRQ (VA_MISC_BASE + 0x218)
45 #define SPEAR1340_PLL2_CTR (VA_MISC_BASE + 0x220)
46 #define SPEAR1340_PLL2_FRQ (VA_MISC_BASE + 0x224)
47 #define SPEAR1340_PLL3_CTR (VA_MISC_BASE + 0x22C)
48 #define SPEAR1340_PLL3_FRQ (VA_MISC_BASE + 0x230)
49 #define SPEAR1340_PLL4_CTR (VA_MISC_BASE + 0x238)
50 #define SPEAR1340_PLL4_FRQ (VA_MISC_BASE + 0x23C)
51 #define SPEAR1340_PERIP_CLK_CFG (VA_MISC_BASE + 0x244)
52  /* PERIP_CLK_CFG bit values */
53  #define SPEAR1340_SPDIF_CLK_MASK 1
54  #define SPEAR1340_SPDIF_OUT_CLK_SHIFT 15
55  #define SPEAR1340_SPDIF_IN_CLK_SHIFT 14
56  #define SPEAR1340_GPT3_CLK_SHIFT 13
57  #define SPEAR1340_GPT2_CLK_SHIFT 12
58  #define SPEAR1340_GPT_CLK_MASK 1
59  #define SPEAR1340_GPT1_CLK_SHIFT 9
60  #define SPEAR1340_GPT0_CLK_SHIFT 8
61  #define SPEAR1340_UART_CLK_MASK 2
62  #define SPEAR1340_UART1_CLK_SHIFT 6
63  #define SPEAR1340_UART0_CLK_SHIFT 4
64  #define SPEAR1340_CLCD_CLK_MASK 2
65  #define SPEAR1340_CLCD_CLK_SHIFT 2
66  #define SPEAR1340_C3_CLK_MASK 1
67  #define SPEAR1340_C3_CLK_SHIFT 1
68 
69 #define SPEAR1340_GMAC_CLK_CFG (VA_MISC_BASE + 0x248)
70  #define SPEAR1340_GMAC_PHY_CLK_MASK 1
71  #define SPEAR1340_GMAC_PHY_CLK_SHIFT 2
72  #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2
73  #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0
74 
75 #define SPEAR1340_I2S_CLK_CFG (VA_MISC_BASE + 0x24C)
76  /* I2S_CLK_CFG register mask */
77  #define SPEAR1340_I2S_SCLK_X_MASK 0x1F
78  #define SPEAR1340_I2S_SCLK_X_SHIFT 27
79  #define SPEAR1340_I2S_SCLK_Y_MASK 0x1F
80  #define SPEAR1340_I2S_SCLK_Y_SHIFT 22
81  #define SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT 21
82  #define SPEAR1340_I2S_SCLK_SYNTH_ENB 20
83  #define SPEAR1340_I2S_PRS1_CLK_X_MASK 0xFF
84  #define SPEAR1340_I2S_PRS1_CLK_X_SHIFT 12
85  #define SPEAR1340_I2S_PRS1_CLK_Y_MASK 0xFF
86  #define SPEAR1340_I2S_PRS1_CLK_Y_SHIFT 4
87  #define SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT 3
88  #define SPEAR1340_I2S_REF_SEL_MASK 1
89  #define SPEAR1340_I2S_REF_SHIFT 2
90  #define SPEAR1340_I2S_SRC_CLK_MASK 2
91  #define SPEAR1340_I2S_SRC_CLK_SHIFT 0
92 
93 #define SPEAR1340_C3_CLK_SYNT (VA_MISC_BASE + 0x250)
94 #define SPEAR1340_UART0_CLK_SYNT (VA_MISC_BASE + 0x254)
95 #define SPEAR1340_UART1_CLK_SYNT (VA_MISC_BASE + 0x258)
96 #define SPEAR1340_GMAC_CLK_SYNT (VA_MISC_BASE + 0x25C)
97 #define SPEAR1340_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x260)
98 #define SPEAR1340_CFXD_CLK_SYNT (VA_MISC_BASE + 0x264)
99 #define SPEAR1340_ADC_CLK_SYNT (VA_MISC_BASE + 0x270)
100 #define SPEAR1340_AMBA_CLK_SYNT (VA_MISC_BASE + 0x274)
101 #define SPEAR1340_CLCD_CLK_SYNT (VA_MISC_BASE + 0x27C)
102 #define SPEAR1340_SYS_CLK_SYNT (VA_MISC_BASE + 0x284)
103 #define SPEAR1340_GEN_CLK_SYNT0 (VA_MISC_BASE + 0x28C)
104 #define SPEAR1340_GEN_CLK_SYNT1 (VA_MISC_BASE + 0x294)
105 #define SPEAR1340_GEN_CLK_SYNT2 (VA_MISC_BASE + 0x29C)
106 #define SPEAR1340_GEN_CLK_SYNT3 (VA_MISC_BASE + 0x304)
107 #define SPEAR1340_PERIP1_CLK_ENB (VA_MISC_BASE + 0x30C)
108  #define SPEAR1340_RTC_CLK_ENB 31
109  #define SPEAR1340_ADC_CLK_ENB 30
110  #define SPEAR1340_C3_CLK_ENB 29
111  #define SPEAR1340_CLCD_CLK_ENB 27
112  #define SPEAR1340_DMA_CLK_ENB 25
113  #define SPEAR1340_GPIO1_CLK_ENB 24
114  #define SPEAR1340_GPIO0_CLK_ENB 23
115  #define SPEAR1340_GPT1_CLK_ENB 22
116  #define SPEAR1340_GPT0_CLK_ENB 21
117  #define SPEAR1340_I2S_PLAY_CLK_ENB 20
118  #define SPEAR1340_I2S_REC_CLK_ENB 19
119  #define SPEAR1340_I2C0_CLK_ENB 18
120  #define SPEAR1340_SSP_CLK_ENB 17
121  #define SPEAR1340_UART0_CLK_ENB 15
122  #define SPEAR1340_PCIE_SATA_CLK_ENB 12
123  #define SPEAR1340_UOC_CLK_ENB 11
124  #define SPEAR1340_UHC1_CLK_ENB 10
125  #define SPEAR1340_UHC0_CLK_ENB 9
126  #define SPEAR1340_GMAC_CLK_ENB 8
127  #define SPEAR1340_CFXD_CLK_ENB 7
128  #define SPEAR1340_SDHCI_CLK_ENB 6
129  #define SPEAR1340_SMI_CLK_ENB 5
130  #define SPEAR1340_FSMC_CLK_ENB 4
131  #define SPEAR1340_SYSRAM0_CLK_ENB 3
132  #define SPEAR1340_SYSRAM1_CLK_ENB 2
133  #define SPEAR1340_SYSROM_CLK_ENB 1
134  #define SPEAR1340_BUS_CLK_ENB 0
135 
136 #define SPEAR1340_PERIP2_CLK_ENB (VA_MISC_BASE + 0x310)
137  #define SPEAR1340_THSENS_CLK_ENB 8
138  #define SPEAR1340_I2S_REF_PAD_CLK_ENB 7
139  #define SPEAR1340_ACP_CLK_ENB 6
140  #define SPEAR1340_GPT3_CLK_ENB 5
141  #define SPEAR1340_GPT2_CLK_ENB 4
142  #define SPEAR1340_KBD_CLK_ENB 3
143  #define SPEAR1340_CPU_DBG_CLK_ENB 2
144  #define SPEAR1340_DDR_CORE_CLK_ENB 1
145  #define SPEAR1340_DDR_CTRL_CLK_ENB 0
146 
147 #define SPEAR1340_PERIP3_CLK_ENB (VA_MISC_BASE + 0x314)
148  #define SPEAR1340_PLGPIO_CLK_ENB 18
149  #define SPEAR1340_VIDEO_DEC_CLK_ENB 16
150  #define SPEAR1340_VIDEO_ENC_CLK_ENB 15
151  #define SPEAR1340_SPDIF_OUT_CLK_ENB 13
152  #define SPEAR1340_SPDIF_IN_CLK_ENB 12
153  #define SPEAR1340_VIDEO_IN_CLK_ENB 11
154  #define SPEAR1340_CAM0_CLK_ENB 10
155  #define SPEAR1340_CAM1_CLK_ENB 9
156  #define SPEAR1340_CAM2_CLK_ENB 8
157  #define SPEAR1340_CAM3_CLK_ENB 7
158  #define SPEAR1340_MALI_CLK_ENB 6
159  #define SPEAR1340_CEC0_CLK_ENB 5
160  #define SPEAR1340_CEC1_CLK_ENB 4
161  #define SPEAR1340_PWM_CLK_ENB 3
162  #define SPEAR1340_I2C1_CLK_ENB 2
163  #define SPEAR1340_UART1_CLK_ENB 1
164 
165 static DEFINE_SPINLOCK(_lock);
166 
167 /* pll rate configuration table, in ascending order of rates */
168 static struct pll_rate_tbl pll_rtbl[] = {
169  /* PCLK 24MHz */
170  {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
171  {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
172  {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
173  {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
174  {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
175  {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
176  {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
177  {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
178 };
179 
180 /* vco-pll4 rate configuration table, in ascending order of rates */
181 static struct pll_rate_tbl pll4_rtbl[] = {
182  {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
183  {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
184  {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
185  {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
186 };
187 
188 /*
189  * All below entries generate 166 MHz for
190  * different values of vco1div2
191  */
192 static struct frac_rate_tbl amba_synth_rtbl[] = {
193  {.div = 0x06062}, /* for vco1div2 = 500 MHz */
194  {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
195  {.div = 0x04000}, /* for vco1div2 = 332 MHz */
196  {.div = 0x03031}, /* for vco1div2 = 250 MHz */
197  {.div = 0x0268D}, /* for vco1div2 = 200 MHz */
198 };
199 
200 /*
201  * Synthesizer Clock derived from vcodiv2. This clock is one of the
202  * possible clocks to feed cpu directly.
203  * We can program this synthesizer to make cpu run on different clock
204  * frequencies.
205  * Following table provides configuration values to let cpu run on 200,
206  * 250, 332, 400 or 500 MHz considering different possibilites of input
207  * (vco1div2) clock.
208  *
209  * --------------------------------------------------------------------
210  * vco1div2(Mhz) fout(Mhz) cpuclk = fout/2 div
211  * --------------------------------------------------------------------
212  * 400 200 100 0x04000
213  * 400 250 125 0x03333
214  * 400 332 166 0x0268D
215  * 400 400 200 0x02000
216  * --------------------------------------------------------------------
217  * 500 200 100 0x05000
218  * 500 250 125 0x04000
219  * 500 332 166 0x03031
220  * 500 400 200 0x02800
221  * 500 500 250 0x02000
222  * --------------------------------------------------------------------
223  * 664 200 100 0x06a38
224  * 664 250 125 0x054FD
225  * 664 332 166 0x04000
226  * 664 400 200 0x0351E
227  * 664 500 250 0x02A7E
228  * --------------------------------------------------------------------
229  * 800 200 100 0x08000
230  * 800 250 125 0x06666
231  * 800 332 166 0x04D18
232  * 800 400 200 0x04000
233  * 800 500 250 0x03333
234  * --------------------------------------------------------------------
235  * sys rate configuration table is in descending order of divisor.
236  */
237 static struct frac_rate_tbl sys_synth_rtbl[] = {
238  {.div = 0x08000},
239  {.div = 0x06a38},
240  {.div = 0x06666},
241  {.div = 0x054FD},
242  {.div = 0x05000},
243  {.div = 0x04D18},
244  {.div = 0x04000},
245  {.div = 0x0351E},
246  {.div = 0x03333},
247  {.div = 0x03031},
248  {.div = 0x02A7E},
249  {.div = 0x02800},
250  {.div = 0x0268D},
251  {.div = 0x02000},
252 };
253 
254 /* aux rate configuration table, in ascending order of rates */
255 static struct aux_rate_tbl aux_rtbl[] = {
256  /* For VCO1div2 = 500 MHz */
257  {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
258  {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
259  {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
260  {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
261  {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
262  {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
263 };
264 
265 /* gmac rate configuration table, in ascending order of rates */
266 static struct aux_rate_tbl gmac_rtbl[] = {
267  /* For gmac phy input clk */
268  {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
269  {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
270  {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
271  {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
272 };
273 
274 /* clcd rate configuration table, in ascending order of rates */
275 static struct frac_rate_tbl clcd_rtbl[] = {
276  {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
277  {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
278  {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
279  {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
280  {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
281  {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/
282  {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
283  {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
284  {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
285  {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
286  {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
287  {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/
288  {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/
289 };
290 
291 /* i2s prescaler1 masks */
292 static struct aux_clk_masks i2s_prs1_masks = {
293  .eq_sel_mask = AUX_EQ_SEL_MASK,
294  .eq_sel_shift = SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT,
295  .eq1_mask = AUX_EQ1_SEL,
296  .eq2_mask = AUX_EQ2_SEL,
297  .xscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_X_MASK,
298  .xscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_X_SHIFT,
299  .yscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_Y_MASK,
300  .yscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_Y_SHIFT,
301 };
302 
303 /* i2s sclk (bit clock) syynthesizers masks */
304 static struct aux_clk_masks i2s_sclk_masks = {
305  .eq_sel_mask = AUX_EQ_SEL_MASK,
306  .eq_sel_shift = SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT,
307  .eq1_mask = AUX_EQ1_SEL,
308  .eq2_mask = AUX_EQ2_SEL,
309  .xscale_sel_mask = SPEAR1340_I2S_SCLK_X_MASK,
310  .xscale_sel_shift = SPEAR1340_I2S_SCLK_X_SHIFT,
311  .yscale_sel_mask = SPEAR1340_I2S_SCLK_Y_MASK,
312  .yscale_sel_shift = SPEAR1340_I2S_SCLK_Y_SHIFT,
313  .enable_bit = SPEAR1340_I2S_SCLK_SYNTH_ENB,
314 };
315 
316 /* i2s prs1 aux rate configuration table, in ascending order of rates */
317 static struct aux_rate_tbl i2s_prs1_rtbl[] = {
318  /* For parent clk = 49.152 MHz */
319  {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
320  {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
321  {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
322  {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
323 
324  /*
325  * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
326  * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
327  */
328  {.xscale = 1, .yscale = 3, .eq = 0},
329 
330  /* For parent clk = 49.152 MHz */
331  {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
332  {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz, smp freq = 48Khz*/
333 };
334 
335 /* i2s sclk aux rate configuration table, in ascending order of rates */
336 static struct aux_rate_tbl i2s_sclk_rtbl[] = {
337  /* For sclk = ref_clk * x/2/y */
338  {.xscale = 1, .yscale = 4, .eq = 0},
339  {.xscale = 1, .yscale = 2, .eq = 0},
340 };
341 
342 /* adc rate configuration table, in ascending order of rates */
343 /* possible adc range is 2.5 MHz to 20 MHz. */
344 static struct aux_rate_tbl adc_rtbl[] = {
345  /* For ahb = 166.67 MHz */
346  {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
347  {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
348  {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
349  {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
350 };
351 
352 /* General synth rate configuration table, in ascending order of rates */
353 static struct frac_rate_tbl gen_rtbl[] = {
354  /* For vco1div4 = 250 MHz */
355  {.div = 0x1624E}, /* 22.5792 MHz */
356  {.div = 0x14585}, /* 24.576 MHz */
357  {.div = 0x14000}, /* 25 MHz */
358  {.div = 0x0B127}, /* 45.1584 MHz */
359  {.div = 0x0A000}, /* 50 MHz */
360  {.div = 0x061A8}, /* 81.92 MHz */
361  {.div = 0x05000}, /* 100 MHz */
362  {.div = 0x02800}, /* 200 MHz */
363  {.div = 0x02620}, /* 210 MHz */
364  {.div = 0x02460}, /* 220 MHz */
365  {.div = 0x022C0}, /* 230 MHz */
366  {.div = 0x02160}, /* 240 MHz */
367  {.div = 0x02000}, /* 250 MHz */
368 };
369 
370 /* clock parents */
371 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
372 static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk",
373  "pll1_clk", "sys_synth_clk", "sys_synth_clk", "pll2_clk", "pll3_clk", };
374 static const char *ahb_parents[] = { "cpu_div3_clk", "amba_syn_clk", };
375 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
376 static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",
377  "uart0_syn_gclk", };
378 static const char *uart1_parents[] = { "pll5_clk", "osc_24m_clk",
379  "uart1_syn_gclk", };
380 static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", };
381 static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk",
382  "osc_25m_clk", };
383 static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", };
384 static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
385 static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", };
386 static const char *i2s_src_parents[] = { "vco1div2_clk", "pll2_clk", "pll3_clk",
387  "i2s_src_pad_clk", };
388 static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", };
389 static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_syn2_clk", };
390 static const char *spdif_in_parents[] = { "pll2_clk", "gen_syn3_clk", };
391 
392 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
393  "pll3_clk", };
394 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
395  "pll2_clk", };
396 
397 void __init spear1340_clk_init(void)
398 {
399  struct clk *clk, *clk1;
400 
401  clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
402  clk_register_clkdev(clk, "apb_pclk", NULL);
403 
404  clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
405  32000);
406  clk_register_clkdev(clk, "osc_32k_clk", NULL);
407 
408  clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
409  24000000);
410  clk_register_clkdev(clk, "osc_24m_clk", NULL);
411 
412  clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
413  25000000);
414  clk_register_clkdev(clk, "osc_25m_clk", NULL);
415 
416  clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT,
417  125000000);
418  clk_register_clkdev(clk, "gmii_pad_clk", NULL);
419 
420  clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
421  CLK_IS_ROOT, 12288000);
422  clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
423 
424  /* clock derived from 32 KHz osc clk */
425  clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
426  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0,
427  &_lock);
428  clk_register_clkdev(clk, NULL, "fc900000.rtc");
429 
430  /* clock derived from 24 or 25 MHz osc clk */
431  /* vco-pll */
432  clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
433  ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
434  SPEAR1340_PLL1_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
435  &_lock);
436  clk_register_clkdev(clk, "vco1_mclk", NULL);
437  clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0,
438  SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl,
439  ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
440  clk_register_clkdev(clk, "vco1_clk", NULL);
441  clk_register_clkdev(clk1, "pll1_clk", NULL);
442 
443  clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
444  ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
445  SPEAR1340_PLL2_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
446  &_lock);
447  clk_register_clkdev(clk, "vco2_mclk", NULL);
448  clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0,
449  SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl,
450  ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
451  clk_register_clkdev(clk, "vco2_clk", NULL);
452  clk_register_clkdev(clk1, "pll2_clk", NULL);
453 
454  clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
455  ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG,
456  SPEAR1340_PLL3_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0,
457  &_lock);
458  clk_register_clkdev(clk, "vco3_mclk", NULL);
459  clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0,
460  SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl,
461  ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
462  clk_register_clkdev(clk, "vco3_clk", NULL);
463  clk_register_clkdev(clk1, "pll3_clk", NULL);
464 
465  clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
466  0, SPEAR1340_PLL4_CTR, SPEAR1340_PLL4_FRQ, pll4_rtbl,
467  ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
468  clk_register_clkdev(clk, "vco4_clk", NULL);
469  clk_register_clkdev(clk1, "pll4_clk", NULL);
470 
471  clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
472  48000000);
473  clk_register_clkdev(clk, "pll5_clk", NULL);
474 
475  clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
476  25000000);
477  clk_register_clkdev(clk, "pll6_clk", NULL);
478 
479  /* vco div n clocks */
480  clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
481  2);
482  clk_register_clkdev(clk, "vco1div2_clk", NULL);
483 
484  clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
485  4);
486  clk_register_clkdev(clk, "vco1div4_clk", NULL);
487 
488  clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
489  2);
490  clk_register_clkdev(clk, "vco2div2_clk", NULL);
491 
492  clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
493  2);
494  clk_register_clkdev(clk, "vco3div2_clk", NULL);
495 
496  /* peripherals */
497  clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
498  128);
499  clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
500  SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0,
501  &_lock);
502  clk_register_clkdev(clk, NULL, "spear_thermal");
503 
504  /* clock derived from pll4 clk */
505  clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
506  1);
507  clk_register_clkdev(clk, "ddr_clk", NULL);
508 
509  /* clock derived from pll1 clk */
510  clk = clk_register_frac("sys_syn_clk", "vco1div2_clk", 0,
511  SPEAR1340_SYS_CLK_SYNT, sys_synth_rtbl,
512  ARRAY_SIZE(sys_synth_rtbl), &_lock);
513  clk_register_clkdev(clk, "sys_syn_clk", NULL);
514 
515  clk = clk_register_frac("amba_syn_clk", "vco1div2_clk", 0,
516  SPEAR1340_AMBA_CLK_SYNT, amba_synth_rtbl,
517  ARRAY_SIZE(amba_synth_rtbl), &_lock);
518  clk_register_clkdev(clk, "amba_syn_clk", NULL);
519 
520  clk = clk_register_mux(NULL, "sys_mclk", sys_parents,
521  ARRAY_SIZE(sys_parents), 0, SPEAR1340_SYS_CLK_CTRL,
522  SPEAR1340_SCLK_SRC_SEL_SHIFT,
523  SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
524  clk_register_clkdev(clk, "sys_clk", NULL);
525 
526  clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1,
527  2);
528  clk_register_clkdev(clk, "cpu_clk", NULL);
529 
530  clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1,
531  3);
532  clk_register_clkdev(clk, "cpu_div3_clk", NULL);
533 
534  clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
535  2);
536  clk_register_clkdev(clk, NULL, "ec800620.wdt");
537 
538  clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
539  ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL,
540  SPEAR1340_HCLK_SRC_SEL_SHIFT,
541  SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock);
542  clk_register_clkdev(clk, "ahb_clk", NULL);
543 
544  clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
545  2);
546  clk_register_clkdev(clk, "apb_clk", NULL);
547 
548  /* gpt clocks */
549  clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
550  ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
551  SPEAR1340_GPT0_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
552  &_lock);
553  clk_register_clkdev(clk, "gpt0_mclk", NULL);
554  clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
555  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0,
556  &_lock);
557  clk_register_clkdev(clk, NULL, "gpt0");
558 
559  clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
560  ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
561  SPEAR1340_GPT1_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
562  &_lock);
563  clk_register_clkdev(clk, "gpt1_mclk", NULL);
564  clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
565  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0,
566  &_lock);
567  clk_register_clkdev(clk, NULL, "gpt1");
568 
569  clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
570  ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
571  SPEAR1340_GPT2_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
572  &_lock);
573  clk_register_clkdev(clk, "gpt2_mclk", NULL);
574  clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
575  SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0,
576  &_lock);
577  clk_register_clkdev(clk, NULL, "gpt2");
578 
579  clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
580  ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG,
581  SPEAR1340_GPT3_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0,
582  &_lock);
583  clk_register_clkdev(clk, "gpt3_mclk", NULL);
584  clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
585  SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0,
586  &_lock);
587  clk_register_clkdev(clk, NULL, "gpt3");
588 
589  /* others */
590  clk = clk_register_aux("uart0_syn_clk", "uart0_syn_gclk",
591  "vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL,
592  aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
593  clk_register_clkdev(clk, "uart0_syn_clk", NULL);
594  clk_register_clkdev(clk1, "uart0_syn_gclk", NULL);
595 
596  clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
597  ARRAY_SIZE(uart0_parents), 0, SPEAR1340_PERIP_CLK_CFG,
598  SPEAR1340_UART0_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
599  &_lock);
600  clk_register_clkdev(clk, "uart0_mclk", NULL);
601 
602  clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", 0,
603  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART0_CLK_ENB, 0,
604  &_lock);
605  clk_register_clkdev(clk, NULL, "e0000000.serial");
606 
607  clk = clk_register_aux("uart1_syn_clk", "uart1_syn_gclk",
608  "vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL,
609  aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
610  clk_register_clkdev(clk, "uart1_syn_clk", NULL);
611  clk_register_clkdev(clk1, "uart1_syn_gclk", NULL);
612 
613  clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents,
614  ARRAY_SIZE(uart1_parents), 0, SPEAR1340_PERIP_CLK_CFG,
615  SPEAR1340_UART1_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0,
616  &_lock);
617  clk_register_clkdev(clk, "uart1_mclk", NULL);
618 
619  clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
620  SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0,
621  &_lock);
622  clk_register_clkdev(clk, NULL, "b4100000.serial");
623 
624  clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
625  "vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL,
626  aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
627  clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
628  clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
629 
630  clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", 0,
631  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SDHCI_CLK_ENB, 0,
632  &_lock);
633  clk_register_clkdev(clk, NULL, "b3000000.sdhci");
634 
635  clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
636  0, SPEAR1340_CFXD_CLK_SYNT, NULL, aux_rtbl,
637  ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
638  clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
639  clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
640 
641  clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", 0,
642  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CFXD_CLK_ENB, 0,
643  &_lock);
644  clk_register_clkdev(clk, NULL, "b2800000.cf");
645  clk_register_clkdev(clk, NULL, "arasan_xd");
646 
647  clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 0,
648  SPEAR1340_C3_CLK_SYNT, NULL, aux_rtbl,
649  ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
650  clk_register_clkdev(clk, "c3_syn_clk", NULL);
651  clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
652 
653  clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
654  ARRAY_SIZE(c3_parents), 0, SPEAR1340_PERIP_CLK_CFG,
655  SPEAR1340_C3_CLK_SHIFT, SPEAR1340_C3_CLK_MASK, 0,
656  &_lock);
657  clk_register_clkdev(clk, "c3_mclk", NULL);
658 
659  clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0,
660  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0,
661  &_lock);
662  clk_register_clkdev(clk, NULL, "c3");
663 
664  /* gmac */
665  clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
666  ARRAY_SIZE(gmac_phy_input_parents), 0,
667  SPEAR1340_GMAC_CLK_CFG,
668  SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT,
669  SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
670  clk_register_clkdev(clk, "phy_input_mclk", NULL);
671 
672  clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk",
673  0, SPEAR1340_GMAC_CLK_SYNT, NULL, gmac_rtbl,
674  ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
675  clk_register_clkdev(clk, "phy_syn_clk", NULL);
676  clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
677 
678  clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
679  ARRAY_SIZE(gmac_phy_parents), 0,
680  SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
681  SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
682  clk_register_clkdev(clk, NULL, "stmmacphy.0");
683 
684  /* clcd */
685  clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
686  ARRAY_SIZE(clcd_synth_parents), 0,
687  SPEAR1340_CLCD_CLK_SYNT, SPEAR1340_CLCD_SYNT_CLK_SHIFT,
688  SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock);
689  clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
690 
691  clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
692  SPEAR1340_CLCD_CLK_SYNT, clcd_rtbl,
693  ARRAY_SIZE(clcd_rtbl), &_lock);
694  clk_register_clkdev(clk, "clcd_syn_clk", NULL);
695 
696  clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
697  ARRAY_SIZE(clcd_pixel_parents), 0,
698  SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
699  SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
700  clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
701 
702  clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
703  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0,
704  &_lock);
705  clk_register_clkdev(clk, "clcd_clk", NULL);
706 
707  /* i2s */
708  clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
709  ARRAY_SIZE(i2s_src_parents), 0, SPEAR1340_I2S_CLK_CFG,
710  SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK,
711  0, &_lock);
712  clk_register_clkdev(clk, "i2s_src_clk", NULL);
713 
714  clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
715  SPEAR1340_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
716  ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
717  clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
718 
719  clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
720  ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1340_I2S_CLK_CFG,
721  SPEAR1340_I2S_REF_SHIFT, SPEAR1340_I2S_REF_SEL_MASK, 0,
722  &_lock);
723  clk_register_clkdev(clk, "i2s_ref_clk", NULL);
724 
725  clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
726  SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB,
727  0, &_lock);
728  clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
729 
730  clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", "i2s_ref_mclk",
731  0, SPEAR1340_I2S_CLK_CFG, &i2s_sclk_masks,
732  i2s_sclk_rtbl, ARRAY_SIZE(i2s_sclk_rtbl), &_lock,
733  &clk1);
734  clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
735  clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL);
736 
737  /* clock derived from ahb clk */
738  clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
739  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C0_CLK_ENB, 0,
740  &_lock);
741  clk_register_clkdev(clk, NULL, "e0280000.i2c");
742 
743  clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0,
744  SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0,
745  &_lock);
746  clk_register_clkdev(clk, NULL, "b4000000.i2c");
747 
748  clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
749  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_DMA_CLK_ENB, 0,
750  &_lock);
751  clk_register_clkdev(clk, NULL, "ea800000.dma");
752  clk_register_clkdev(clk, NULL, "eb000000.dma");
753 
754  clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
755  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GMAC_CLK_ENB, 0,
756  &_lock);
757  clk_register_clkdev(clk, NULL, "e2000000.eth");
758 
759  clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
760  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_FSMC_CLK_ENB, 0,
761  &_lock);
762  clk_register_clkdev(clk, NULL, "b0000000.flash");
763 
764  clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
765  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SMI_CLK_ENB, 0,
766  &_lock);
767  clk_register_clkdev(clk, NULL, "ea000000.flash");
768 
769  clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
770  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0,
771  &_lock);
772  clk_register_clkdev(clk, "usbh.0_clk", NULL);
773 
774  clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
775  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0,
776  &_lock);
777  clk_register_clkdev(clk, "usbh.1_clk", NULL);
778 
779  clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
780  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0,
781  &_lock);
782  clk_register_clkdev(clk, NULL, "uoc");
783 
784  clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
785  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
786  0, &_lock);
787  clk_register_clkdev(clk, NULL, "dw_pcie");
788  clk_register_clkdev(clk, NULL, "ahci");
789 
790  clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
791  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0,
792  &_lock);
793  clk_register_clkdev(clk, "sysram0_clk", NULL);
794 
795  clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
796  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM1_CLK_ENB, 0,
797  &_lock);
798  clk_register_clkdev(clk, "sysram1_clk", NULL);
799 
800  clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
801  0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl,
802  ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
803  clk_register_clkdev(clk, "adc_syn_clk", NULL);
804  clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
805 
806  clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 0,
807  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_ADC_CLK_ENB, 0,
808  &_lock);
809  clk_register_clkdev(clk, NULL, "adc_clk");
810 
811  /* clock derived from apb clk */
812  clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0,
813  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SSP_CLK_ENB, 0,
814  &_lock);
815  clk_register_clkdev(clk, NULL, "e0100000.spi");
816 
817  clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
818  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO0_CLK_ENB, 0,
819  &_lock);
820  clk_register_clkdev(clk, NULL, "e0600000.gpio");
821 
822  clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
823  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO1_CLK_ENB, 0,
824  &_lock);
825  clk_register_clkdev(clk, NULL, "e0680000.gpio");
826 
827  clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0,
828  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0,
829  &_lock);
830  clk_register_clkdev(clk, NULL, "b2400000.i2s");
831 
832  clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0,
833  SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0,
834  &_lock);
835  clk_register_clkdev(clk, NULL, "b2000000.i2s");
836 
837  clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
838  SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0,
839  &_lock);
840  clk_register_clkdev(clk, NULL, "e0300000.kbd");
841 
842  /* RAS clks */
843  clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
844  ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1340_PLL_CFG,
845  SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
846  SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
847  clk_register_clkdev(clk, "gen_syn0_1_clk", NULL);
848 
849  clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
850  ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1340_PLL_CFG,
851  SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
852  SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
853  clk_register_clkdev(clk, "gen_syn2_3_clk", NULL);
854 
855  clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0,
856  SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
857  &_lock);
858  clk_register_clkdev(clk, "gen_syn0_clk", NULL);
859 
860  clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0,
861  SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
862  &_lock);
863  clk_register_clkdev(clk, "gen_syn1_clk", NULL);
864 
865  clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0,
866  SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
867  &_lock);
868  clk_register_clkdev(clk, "gen_syn2_clk", NULL);
869 
870  clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0,
871  SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
872  &_lock);
873  clk_register_clkdev(clk, "gen_syn3_clk", NULL);
874 
875  clk = clk_register_gate(NULL, "mali_clk", "gen_syn3_clk", 0,
876  SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_MALI_CLK_ENB, 0,
877  &_lock);
878  clk_register_clkdev(clk, NULL, "mali");
879 
880  clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0,
881  SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC0_CLK_ENB, 0,
882  &_lock);
883  clk_register_clkdev(clk, NULL, "spear_cec.0");
884 
885  clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0,
886  SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC1_CLK_ENB, 0,
887  &_lock);
888  clk_register_clkdev(clk, NULL, "spear_cec.1");
889 
890  clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents,
891  ARRAY_SIZE(spdif_out_parents), 0,
892  SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
893  SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
894  clk_register_clkdev(clk, "spdif_out_mclk", NULL);
895 
896  clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mclk", 0,
897  SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_OUT_CLK_ENB,
898  0, &_lock);
899  clk_register_clkdev(clk, NULL, "spdif-out");
900 
901  clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents,
902  ARRAY_SIZE(spdif_in_parents), 0,
903  SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
904  SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
905  clk_register_clkdev(clk, "spdif_in_mclk", NULL);
906 
907  clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mclk", 0,
908  SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_IN_CLK_ENB, 0,
909  &_lock);
910  clk_register_clkdev(clk, NULL, "spdif-in");
911 
912  clk = clk_register_gate(NULL, "acp_clk", "acp_mclk", 0,
913  SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
914  &_lock);
915  clk_register_clkdev(clk, NULL, "acp_clk");
916 
917  clk = clk_register_gate(NULL, "plgpio_clk", "plgpio_mclk", 0,
918  SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
919  &_lock);
920  clk_register_clkdev(clk, NULL, "plgpio");
921 
922  clk = clk_register_gate(NULL, "video_dec_clk", "video_dec_mclk", 0,
923  SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
924  0, &_lock);
925  clk_register_clkdev(clk, NULL, "video_dec");
926 
927  clk = clk_register_gate(NULL, "video_enc_clk", "video_enc_mclk", 0,
928  SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
929  0, &_lock);
930  clk_register_clkdev(clk, NULL, "video_enc");
931 
932  clk = clk_register_gate(NULL, "video_in_clk", "video_in_mclk", 0,
933  SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
934  &_lock);
935  clk_register_clkdev(clk, NULL, "spear_vip");
936 
937  clk = clk_register_gate(NULL, "cam0_clk", "cam0_mclk", 0,
938  SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
939  &_lock);
940  clk_register_clkdev(clk, NULL, "spear_camif.0");
941 
942  clk = clk_register_gate(NULL, "cam1_clk", "cam1_mclk", 0,
943  SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
944  &_lock);
945  clk_register_clkdev(clk, NULL, "spear_camif.1");
946 
947  clk = clk_register_gate(NULL, "cam2_clk", "cam2_mclk", 0,
948  SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
949  &_lock);
950  clk_register_clkdev(clk, NULL, "spear_camif.2");
951 
952  clk = clk_register_gate(NULL, "cam3_clk", "cam3_mclk", 0,
953  SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
954  &_lock);
955  clk_register_clkdev(clk, NULL, "spear_camif.3");
956 
957  clk = clk_register_gate(NULL, "pwm_clk", "pwm_mclk", 0,
958  SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0,
959  &_lock);
960  clk_register_clkdev(clk, NULL, "pwm");
961 }
Generated on Thu Jan 10 2013 13:28:27 for Linux Kernel by   doxygen 1.8.2