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spear3xx_clock.c
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1 /*
2  * SPEAr3xx machines clock framework source file
3  *
4  * Copyright (C) 2012 ST Microelectronics
5  * Viresh Kumar <[email protected]>
6  *
7  * This file is licensed under the terms of the GNU General Public
8  * License version 2. This program is licensed "as is" without any
9  * warranty of any kind, whether express or implied.
10  */
11 
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/err.h>
15 #include <linux/io.h>
16 #include <linux/of_platform.h>
17 #include <linux/spinlock_types.h>
18 #include <mach/misc_regs.h>
19 #include "clk.h"
20 
21 static DEFINE_SPINLOCK(_lock);
22 
23 #define PLL1_CTR (MISC_BASE + 0x008)
24 #define PLL1_FRQ (MISC_BASE + 0x00C)
25 #define PLL2_CTR (MISC_BASE + 0x014)
26 #define PLL2_FRQ (MISC_BASE + 0x018)
27 #define PLL_CLK_CFG (MISC_BASE + 0x020)
28  /* PLL_CLK_CFG register masks */
29  #define MCTR_CLK_SHIFT 28
30  #define MCTR_CLK_MASK 3
31 
32 #define CORE_CLK_CFG (MISC_BASE + 0x024)
33  /* CORE CLK CFG register masks */
34  #define GEN_SYNTH2_3_CLK_SHIFT 18
35  #define GEN_SYNTH2_3_CLK_MASK 1
36 
37  #define HCLK_RATIO_SHIFT 10
38  #define HCLK_RATIO_MASK 2
39  #define PCLK_RATIO_SHIFT 8
40  #define PCLK_RATIO_MASK 2
41 
42 #define PERIP_CLK_CFG (MISC_BASE + 0x028)
43  /* PERIP_CLK_CFG register masks */
44  #define UART_CLK_SHIFT 4
45  #define UART_CLK_MASK 1
46  #define FIRDA_CLK_SHIFT 5
47  #define FIRDA_CLK_MASK 2
48  #define GPT0_CLK_SHIFT 8
49  #define GPT1_CLK_SHIFT 11
50  #define GPT2_CLK_SHIFT 12
51  #define GPT_CLK_MASK 1
52 
53 #define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
54  /* PERIP1_CLK_ENB register masks */
55  #define UART_CLK_ENB 3
56  #define SSP_CLK_ENB 5
57  #define I2C_CLK_ENB 7
58  #define JPEG_CLK_ENB 8
59  #define FIRDA_CLK_ENB 10
60  #define GPT1_CLK_ENB 11
61  #define GPT2_CLK_ENB 12
62  #define ADC_CLK_ENB 15
63  #define RTC_CLK_ENB 17
64  #define GPIO_CLK_ENB 18
65  #define DMA_CLK_ENB 19
66  #define SMI_CLK_ENB 21
67  #define GMAC_CLK_ENB 23
68  #define USBD_CLK_ENB 24
69  #define USBH_CLK_ENB 25
70  #define C3_CLK_ENB 31
71 
72 #define RAS_CLK_ENB (MISC_BASE + 0x034)
73  #define RAS_AHB_CLK_ENB 0
74  #define RAS_PLL1_CLK_ENB 1
75  #define RAS_APB_CLK_ENB 2
76  #define RAS_32K_CLK_ENB 3
77  #define RAS_24M_CLK_ENB 4
78  #define RAS_48M_CLK_ENB 5
79  #define RAS_PLL2_CLK_ENB 7
80  #define RAS_SYNT0_CLK_ENB 8
81  #define RAS_SYNT1_CLK_ENB 9
82  #define RAS_SYNT2_CLK_ENB 10
83  #define RAS_SYNT3_CLK_ENB 11
84 
85 #define PRSC0_CLK_CFG (MISC_BASE + 0x044)
86 #define PRSC1_CLK_CFG (MISC_BASE + 0x048)
87 #define PRSC2_CLK_CFG (MISC_BASE + 0x04C)
88 #define AMEM_CLK_CFG (MISC_BASE + 0x050)
89  #define AMEM_CLK_ENB 0
90 
91 #define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
92 #define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
93 #define UART_CLK_SYNT (MISC_BASE + 0x064)
94 #define GMAC_CLK_SYNT (MISC_BASE + 0x068)
95 #define GEN0_CLK_SYNT (MISC_BASE + 0x06C)
96 #define GEN1_CLK_SYNT (MISC_BASE + 0x070)
97 #define GEN2_CLK_SYNT (MISC_BASE + 0x074)
98 #define GEN3_CLK_SYNT (MISC_BASE + 0x078)
99 
100 /* pll rate configuration table, in ascending order of rates */
101 static struct pll_rate_tbl pll_rtbl[] = {
102  {.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* vco 332 & pll 166 MHz */
103  {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* vco 532 & pll 266 MHz */
104  {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* vco 664 & pll 332 MHz */
105 };
106 
107 /* aux rate configuration table, in ascending order of rates */
108 static struct aux_rate_tbl aux_rtbl[] = {
109  /* For PLL1 = 332 MHz */
110  {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
111  {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
112  {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
113  {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
114 };
115 
116 /* gpt rate configuration table, in ascending order of rates */
117 static struct gpt_rate_tbl gpt_rtbl[] = {
118  /* For pll1 = 332 MHz */
119  {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
120  {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
121  {.mscale = 1, .nscale = 0}, /* 83 MHz */
122 };
123 
124 /* clock parents */
125 static const char *uart0_parents[] = { "pll3_clk", "uart_syn_gclk", };
126 static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk",
127 };
128 static const char *gpt0_parents[] = { "pll3_clk", "gpt0_syn_clk", };
129 static const char *gpt1_parents[] = { "pll3_clk", "gpt1_syn_clk", };
130 static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
131 static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", };
132 static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
133  "pll2_clk", };
134 
135 #ifdef CONFIG_MACH_SPEAR300
136 static void __init spear300_clk_init(void)
137 {
138  struct clk *clk;
139 
140  clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
141  1, 1);
142  clk_register_clkdev(clk, NULL, "60000000.clcd");
143 
144  clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
145  1);
146  clk_register_clkdev(clk, NULL, "94000000.flash");
147 
148  clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1,
149  1);
150  clk_register_clkdev(clk, NULL, "70000000.sdhci");
151 
152  clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1,
153  1);
154  clk_register_clkdev(clk, NULL, "a9000000.gpio");
155 
156  clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1,
157  1);
158  clk_register_clkdev(clk, NULL, "a0000000.kbd");
159 }
160 #endif
161 
162 /* array of all spear 310 clock lookups */
163 #ifdef CONFIG_MACH_SPEAR310
164 static void __init spear310_clk_init(void)
165 {
166  struct clk *clk;
167 
168  clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
169  1);
170  clk_register_clkdev(clk, "emi", NULL);
171 
172  clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
173  1);
174  clk_register_clkdev(clk, NULL, "44000000.flash");
175 
176  clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1,
177  1);
178  clk_register_clkdev(clk, NULL, "tdm");
179 
180  clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1,
181  1);
182  clk_register_clkdev(clk, NULL, "b2000000.serial");
183 
184  clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1,
185  1);
186  clk_register_clkdev(clk, NULL, "b2080000.serial");
187 
188  clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1,
189  1);
190  clk_register_clkdev(clk, NULL, "b2100000.serial");
191 
192  clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1,
193  1);
194  clk_register_clkdev(clk, NULL, "b2180000.serial");
195 
196  clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1,
197  1);
198  clk_register_clkdev(clk, NULL, "b2200000.serial");
199 }
200 #endif
201 
202 /* array of all spear 320 clock lookups */
203 #ifdef CONFIG_MACH_SPEAR320
204  #define SMII_PCLK_SHIFT 18
205  #define SMII_PCLK_MASK 2
206  #define SMII_PCLK_VAL_PAD 0x0
207  #define SMII_PCLK_VAL_PLL2 0x1
208  #define SMII_PCLK_VAL_SYNTH0 0x2
209  #define SDHCI_PCLK_SHIFT 15
210  #define SDHCI_PCLK_MASK 1
211  #define SDHCI_PCLK_VAL_48M 0x0
212  #define SDHCI_PCLK_VAL_SYNTH3 0x1
213  #define I2S_REF_PCLK_SHIFT 8
214  #define I2S_REF_PCLK_MASK 1
215  #define I2S_REF_PCLK_SYNTH_VAL 0x1
216  #define I2S_REF_PCLK_PLL2_VAL 0x0
217  #define UART1_PCLK_SHIFT 6
218  #define UART1_PCLK_MASK 1
219  #define SPEAR320_UARTX_PCLK_VAL_SYNTH1 0x0
220  #define SPEAR320_UARTX_PCLK_VAL_APB 0x1
221 
222 static const char *i2s_ref_parents[] = { "ras_pll2_clk", "ras_syn2_gclk", };
223 static const char *sdhci_parents[] = { "ras_pll3_clk", "ras_syn3_gclk", };
224 static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
225  "ras_syn0_gclk", };
226 static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };
227 
228 static void __init spear320_clk_init(void)
229 {
230  struct clk *clk;
231 
232  clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL,
233  CLK_IS_ROOT, 125000000);
234  clk_register_clkdev(clk, "smii_125m_pad", NULL);
235 
236  clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
237  1, 1);
238  clk_register_clkdev(clk, NULL, "90000000.clcd");
239 
240  clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
241  1);
242  clk_register_clkdev(clk, "emi", NULL);
243 
244  clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
245  1);
246  clk_register_clkdev(clk, NULL, "4c000000.flash");
247 
248  clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1,
249  1);
250  clk_register_clkdev(clk, NULL, "a7000000.i2c");
251 
252  clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1,
253  1);
254  clk_register_clkdev(clk, "pwm", NULL);
255 
256  clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1,
257  1);
258  clk_register_clkdev(clk, NULL, "a5000000.spi");
259 
260  clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1,
261  1);
262  clk_register_clkdev(clk, NULL, "a6000000.spi");
263 
264  clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1,
265  1);
266  clk_register_clkdev(clk, NULL, "c_can_platform.0");
267 
268  clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1,
269  1);
270  clk_register_clkdev(clk, NULL, "c_can_platform.1");
271 
272  clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1,
273  1);
274  clk_register_clkdev(clk, NULL, "i2s");
275 
276  clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
277  ARRAY_SIZE(i2s_ref_parents), 0, SPEAR320_CONTROL_REG,
278  I2S_REF_PCLK_SHIFT, I2S_REF_PCLK_MASK, 0, &_lock);
279  clk_register_clkdev(clk, "i2s_ref_clk", NULL);
280 
281  clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk", 0, 1,
282  4);
283  clk_register_clkdev(clk, "i2s_sclk", NULL);
284 
285  clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
286  ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
287  SPEAR320_RS485_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
288  &_lock);
289  clk_register_clkdev(clk, NULL, "a9300000.serial");
290 
291  clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
292  ARRAY_SIZE(sdhci_parents), 0, SPEAR320_CONTROL_REG,
293  SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK, 0, &_lock);
294  clk_register_clkdev(clk, NULL, "70000000.sdhci");
295 
296  clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
297  ARRAY_SIZE(smii0_parents), 0, SPEAR320_CONTROL_REG,
298  SMII_PCLK_SHIFT, SMII_PCLK_MASK, 0, &_lock);
299  clk_register_clkdev(clk, NULL, "smii_pclk");
300 
301  clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
302  clk_register_clkdev(clk, NULL, "smii");
303 
304  clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
305  ARRAY_SIZE(uartx_parents), 0, SPEAR320_CONTROL_REG,
306  UART1_PCLK_SHIFT, UART1_PCLK_MASK, 0, &_lock);
307  clk_register_clkdev(clk, NULL, "a3000000.serial");
308 
309  clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
310  ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
311  SPEAR320_UART2_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
312  &_lock);
313  clk_register_clkdev(clk, NULL, "a4000000.serial");
314 
315  clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
316  ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
317  SPEAR320_UART3_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
318  &_lock);
319  clk_register_clkdev(clk, NULL, "a9100000.serial");
320 
321  clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
322  ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
323  SPEAR320_UART4_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
324  &_lock);
325  clk_register_clkdev(clk, NULL, "a9200000.serial");
326 
327  clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
328  ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
329  SPEAR320_UART5_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
330  &_lock);
331  clk_register_clkdev(clk, NULL, "60000000.serial");
332 
333  clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
334  ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
335  SPEAR320_UART6_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
336  &_lock);
337  clk_register_clkdev(clk, NULL, "60100000.serial");
338 }
339 #endif
340 
341 void __init spear3xx_clk_init(void)
342 {
343  struct clk *clk, *clk1;
344 
345  clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
346  clk_register_clkdev(clk, "apb_pclk", NULL);
347 
348  clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
349  32000);
350  clk_register_clkdev(clk, "osc_32k_clk", NULL);
351 
352  clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
353  24000000);
354  clk_register_clkdev(clk, "osc_24m_clk", NULL);
355 
356  /* clock derived from 32 KHz osc clk */
357  clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
358  PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
359  clk_register_clkdev(clk, NULL, "fc900000.rtc");
360 
361  /* clock derived from 24 MHz osc clk */
362  clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
363  48000000);
364  clk_register_clkdev(clk, "pll3_clk", NULL);
365 
366  clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1,
367  1);
368  clk_register_clkdev(clk, NULL, "fc880000.wdt");
369 
370  clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL,
371  "osc_24m_clk", 0, PLL1_CTR, PLL1_FRQ, pll_rtbl,
372  ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
373  clk_register_clkdev(clk, "vco1_clk", NULL);
374  clk_register_clkdev(clk1, "pll1_clk", NULL);
375 
376  clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
377  "osc_24m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl,
378  ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
379  clk_register_clkdev(clk, "vco2_clk", NULL);
380  clk_register_clkdev(clk1, "pll2_clk", NULL);
381 
382  /* clock derived from pll1 clk */
383  clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1);
384  clk_register_clkdev(clk, "cpu_clk", NULL);
385 
386  clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
387  CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
388  HCLK_RATIO_MASK, 0, &_lock);
389  clk_register_clkdev(clk, "ahb_clk", NULL);
390 
391  clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
392  UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
393  &_lock, &clk1);
394  clk_register_clkdev(clk, "uart_syn_clk", NULL);
395  clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
396 
397  clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
398  ARRAY_SIZE(uart0_parents), 0, PERIP_CLK_CFG,
399  UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
400  clk_register_clkdev(clk, "uart0_mclk", NULL);
401 
402  clk = clk_register_gate(NULL, "uart0", "uart0_mclk", 0, PERIP1_CLK_ENB,
403  UART_CLK_ENB, 0, &_lock);
404  clk_register_clkdev(clk, NULL, "d0000000.serial");
405 
406  clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0,
407  FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
408  &_lock, &clk1);
409  clk_register_clkdev(clk, "firda_syn_clk", NULL);
410  clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
411 
412  clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
413  ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
414  FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
415  clk_register_clkdev(clk, "firda_mclk", NULL);
416 
417  clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
418  PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
419  clk_register_clkdev(clk, NULL, "firda");
420 
421  /* gpt clocks */
422  clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl,
423  ARRAY_SIZE(gpt_rtbl), &_lock);
424  clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
425  ARRAY_SIZE(gpt0_parents), 0, PERIP_CLK_CFG,
426  GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
427  clk_register_clkdev(clk, NULL, "gpt0");
428 
429  clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl,
430  ARRAY_SIZE(gpt_rtbl), &_lock);
431  clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
432  ARRAY_SIZE(gpt1_parents), 0, PERIP_CLK_CFG,
433  GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
434  clk_register_clkdev(clk, "gpt1_mclk", NULL);
435  clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
436  PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
437  clk_register_clkdev(clk, NULL, "gpt1");
438 
439  clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl,
440  ARRAY_SIZE(gpt_rtbl), &_lock);
441  clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
442  ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
443  GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
444  clk_register_clkdev(clk, "gpt2_mclk", NULL);
445  clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
446  PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
447  clk_register_clkdev(clk, NULL, "gpt2");
448 
449  /* general synths clocks */
450  clk = clk_register_aux("gen0_syn_clk", "gen0_syn_gclk", "pll1_clk",
451  0, GEN0_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
452  &_lock, &clk1);
453  clk_register_clkdev(clk, "gen0_syn_clk", NULL);
454  clk_register_clkdev(clk1, "gen0_syn_gclk", NULL);
455 
456  clk = clk_register_aux("gen1_syn_clk", "gen1_syn_gclk", "pll1_clk",
457  0, GEN1_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
458  &_lock, &clk1);
459  clk_register_clkdev(clk, "gen1_syn_clk", NULL);
460  clk_register_clkdev(clk1, "gen1_syn_gclk", NULL);
461 
462  clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents,
463  ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG,
464  GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0,
465  &_lock);
466  clk_register_clkdev(clk, "gen2_3_par_clk", NULL);
467 
468  clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk",
469  "gen2_3_par_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl,
470  ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
471  clk_register_clkdev(clk, "gen2_syn_clk", NULL);
472  clk_register_clkdev(clk1, "gen2_syn_gclk", NULL);
473 
474  clk = clk_register_aux("gen3_syn_clk", "gen3_syn_gclk",
475  "gen2_3_par_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl,
476  ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
477  clk_register_clkdev(clk, "gen3_syn_clk", NULL);
478  clk_register_clkdev(clk1, "gen3_syn_gclk", NULL);
479 
480  /* clock derived from pll3 clk */
481  clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
482  USBH_CLK_ENB, 0, &_lock);
483  clk_register_clkdev(clk, "usbh_clk", NULL);
484 
485  clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
486  1);
487  clk_register_clkdev(clk, "usbh.0_clk", NULL);
488 
489  clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1,
490  1);
491  clk_register_clkdev(clk, "usbh.1_clk", NULL);
492 
493  clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
494  USBD_CLK_ENB, 0, &_lock);
495  clk_register_clkdev(clk, NULL, "designware_udc");
496 
497  /* clock derived from ahb clk */
498  clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
499  1);
500  clk_register_clkdev(clk, "ahbmult2_clk", NULL);
501 
502  clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
503  ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT,
504  MCTR_CLK_MASK, 0, &_lock);
505  clk_register_clkdev(clk, "ddr_clk", NULL);
506 
507  clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
508  CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
509  PCLK_RATIO_MASK, 0, &_lock);
510  clk_register_clkdev(clk, "apb_clk", NULL);
511 
512  clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG,
513  AMEM_CLK_ENB, 0, &_lock);
514  clk_register_clkdev(clk, "amem_clk", NULL);
515 
516  clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
517  C3_CLK_ENB, 0, &_lock);
518  clk_register_clkdev(clk, NULL, "c3_clk");
519 
520  clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
521  DMA_CLK_ENB, 0, &_lock);
522  clk_register_clkdev(clk, NULL, "fc400000.dma");
523 
524  clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
525  GMAC_CLK_ENB, 0, &_lock);
526  clk_register_clkdev(clk, NULL, "e0800000.eth");
527 
528  clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
529  I2C_CLK_ENB, 0, &_lock);
530  clk_register_clkdev(clk, NULL, "d0180000.i2c");
531 
532  clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
533  JPEG_CLK_ENB, 0, &_lock);
534  clk_register_clkdev(clk, NULL, "jpeg");
535 
536  clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
537  SMI_CLK_ENB, 0, &_lock);
538  clk_register_clkdev(clk, NULL, "fc000000.flash");
539 
540  /* clock derived from apb clk */
541  clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
542  ADC_CLK_ENB, 0, &_lock);
543  clk_register_clkdev(clk, NULL, "adc");
544 
545  clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
546  GPIO_CLK_ENB, 0, &_lock);
547  clk_register_clkdev(clk, NULL, "fc980000.gpio");
548 
549  clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
550  SSP_CLK_ENB, 0, &_lock);
551  clk_register_clkdev(clk, NULL, "d0100000.spi");
552 
553  /* RAS clk enable */
554  clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB,
555  RAS_AHB_CLK_ENB, 0, &_lock);
556  clk_register_clkdev(clk, "ras_ahb_clk", NULL);
557 
558  clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB,
559  RAS_APB_CLK_ENB, 0, &_lock);
560  clk_register_clkdev(clk, "ras_apb_clk", NULL);
561 
562  clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0,
563  RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock);
564  clk_register_clkdev(clk, "ras_32k_clk", NULL);
565 
566  clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0,
567  RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock);
568  clk_register_clkdev(clk, "ras_24m_clk", NULL);
569 
570  clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0,
571  RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock);
572  clk_register_clkdev(clk, "ras_pll1_clk", NULL);
573 
574  clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
575  RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock);
576  clk_register_clkdev(clk, "ras_pll2_clk", NULL);
577 
578  clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
579  RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock);
580  clk_register_clkdev(clk, "ras_pll3_clk", NULL);
581 
582  clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk", 0,
583  RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0, &_lock);
584  clk_register_clkdev(clk, "ras_syn0_gclk", NULL);
585 
586  clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk", 0,
587  RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0, &_lock);
588  clk_register_clkdev(clk, "ras_syn1_gclk", NULL);
589 
590  clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk", 0,
591  RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0, &_lock);
592  clk_register_clkdev(clk, "ras_syn2_gclk", NULL);
593 
594  clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk", 0,
595  RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0, &_lock);
596  clk_register_clkdev(clk, "ras_syn3_gclk", NULL);
597 
598  if (of_machine_is_compatible("st,spear300"))
599  spear300_clk_init();
600  else if (of_machine_is_compatible("st,spear310"))
601  spear310_clk_init();
602  else if (of_machine_is_compatible("st,spear320"))
603  spear320_clk_init();
604 }
Generated on Thu Jan 10 2013 13:28:27 for Linux Kernel by   doxygen 1.8.2