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spear6xx_clock.c
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1 /*
2  * SPEAr6xx machines clock framework source file
3  *
4  * Copyright (C) 2012 ST Microelectronics
5  * Viresh Kumar <[email protected]>
6  *
7  * This file is licensed under the terms of the GNU General Public
8  * License version 2. This program is licensed "as is" without any
9  * warranty of any kind, whether express or implied.
10  */
11 
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/io.h>
15 #include <linux/spinlock_types.h>
16 #include <mach/misc_regs.h>
17 #include "clk.h"
18 
19 static DEFINE_SPINLOCK(_lock);
20 
21 #define PLL1_CTR (MISC_BASE + 0x008)
22 #define PLL1_FRQ (MISC_BASE + 0x00C)
23 #define PLL2_CTR (MISC_BASE + 0x014)
24 #define PLL2_FRQ (MISC_BASE + 0x018)
25 #define PLL_CLK_CFG (MISC_BASE + 0x020)
26  /* PLL_CLK_CFG register masks */
27  #define MCTR_CLK_SHIFT 28
28  #define MCTR_CLK_MASK 3
29 
30 #define CORE_CLK_CFG (MISC_BASE + 0x024)
31  /* CORE CLK CFG register masks */
32  #define HCLK_RATIO_SHIFT 10
33  #define HCLK_RATIO_MASK 2
34  #define PCLK_RATIO_SHIFT 8
35  #define PCLK_RATIO_MASK 2
36 
37 #define PERIP_CLK_CFG (MISC_BASE + 0x028)
38  /* PERIP_CLK_CFG register masks */
39  #define CLCD_CLK_SHIFT 2
40  #define CLCD_CLK_MASK 2
41  #define UART_CLK_SHIFT 4
42  #define UART_CLK_MASK 1
43  #define FIRDA_CLK_SHIFT 5
44  #define FIRDA_CLK_MASK 2
45  #define GPT0_CLK_SHIFT 8
46  #define GPT1_CLK_SHIFT 10
47  #define GPT2_CLK_SHIFT 11
48  #define GPT3_CLK_SHIFT 12
49  #define GPT_CLK_MASK 1
50 
51 #define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
52  /* PERIP1_CLK_ENB register masks */
53  #define UART0_CLK_ENB 3
54  #define UART1_CLK_ENB 4
55  #define SSP0_CLK_ENB 5
56  #define SSP1_CLK_ENB 6
57  #define I2C_CLK_ENB 7
58  #define JPEG_CLK_ENB 8
59  #define FSMC_CLK_ENB 9
60  #define FIRDA_CLK_ENB 10
61  #define GPT2_CLK_ENB 11
62  #define GPT3_CLK_ENB 12
63  #define GPIO2_CLK_ENB 13
64  #define SSP2_CLK_ENB 14
65  #define ADC_CLK_ENB 15
66  #define GPT1_CLK_ENB 11
67  #define RTC_CLK_ENB 17
68  #define GPIO1_CLK_ENB 18
69  #define DMA_CLK_ENB 19
70  #define SMI_CLK_ENB 21
71  #define CLCD_CLK_ENB 22
72  #define GMAC_CLK_ENB 23
73  #define USBD_CLK_ENB 24
74  #define USBH0_CLK_ENB 25
75  #define USBH1_CLK_ENB 26
76 
77 #define PRSC0_CLK_CFG (MISC_BASE + 0x044)
78 #define PRSC1_CLK_CFG (MISC_BASE + 0x048)
79 #define PRSC2_CLK_CFG (MISC_BASE + 0x04C)
80 
81 #define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
82 #define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
83 #define UART_CLK_SYNT (MISC_BASE + 0x064)
84 
85 /* vco rate configuration table, in ascending order of rates */
86 static struct pll_rate_tbl pll_rtbl[] = {
87  {.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */
88  {.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */
89  {.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */
90 };
91 
92 /* aux rate configuration table, in ascending order of rates */
93 static struct aux_rate_tbl aux_rtbl[] = {
94  /* For PLL1 = 332 MHz */
95  {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
96  {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
97  {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
98 };
99 
100 static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", };
101 static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", };
102 static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", };
103 static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", };
104 static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
105 static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", };
106 static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
107  "pll2_clk", };
108 
109 /* gpt rate configuration table, in ascending order of rates */
110 static struct gpt_rate_tbl gpt_rtbl[] = {
111  /* For pll1 = 332 MHz */
112  {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
113  {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
114  {.mscale = 1, .nscale = 0}, /* 83 MHz */
115 };
116 
117 void __init spear6xx_clk_init(void)
118 {
119  struct clk *clk, *clk1;
120 
121  clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
122  clk_register_clkdev(clk, "apb_pclk", NULL);
123 
124  clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
125  32000);
126  clk_register_clkdev(clk, "osc_32k_clk", NULL);
127 
128  clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, CLK_IS_ROOT,
129  30000000);
130  clk_register_clkdev(clk, "osc_30m_clk", NULL);
131 
132  /* clock derived from 32 KHz osc clk */
133  clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0,
134  PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
135  clk_register_clkdev(clk, NULL, "rtc-spear");
136 
137  /* clock derived from 30 MHz osc clk */
138  clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
139  48000000);
140  clk_register_clkdev(clk, "pll3_clk", NULL);
141 
142  clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
143  0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
144  &_lock, &clk1, NULL);
145  clk_register_clkdev(clk, "vco1_clk", NULL);
146  clk_register_clkdev(clk1, "pll1_clk", NULL);
147 
148  clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk",
149  0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
150  &_lock, &clk1, NULL);
151  clk_register_clkdev(clk, "vco2_clk", NULL);
152  clk_register_clkdev(clk1, "pll2_clk", NULL);
153 
154  clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
155  1);
156  clk_register_clkdev(clk, NULL, "wdt");
157 
158  /* clock derived from pll1 clk */
159  clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1);
160  clk_register_clkdev(clk, "cpu_clk", NULL);
161 
162  clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
163  CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
164  HCLK_RATIO_MASK, 0, &_lock);
165  clk_register_clkdev(clk, "ahb_clk", NULL);
166 
167  clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
168  UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
169  &_lock, &clk1);
170  clk_register_clkdev(clk, "uart_syn_clk", NULL);
171  clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
172 
173  clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
174  ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG,
175  UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
176  clk_register_clkdev(clk, "uart_mclk", NULL);
177 
178  clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
179  UART0_CLK_ENB, 0, &_lock);
180  clk_register_clkdev(clk, NULL, "d0000000.serial");
181 
182  clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
183  UART1_CLK_ENB, 0, &_lock);
184  clk_register_clkdev(clk, NULL, "d0080000.serial");
185 
186  clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk",
187  0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
188  &_lock, &clk1);
189  clk_register_clkdev(clk, "firda_syn_clk", NULL);
190  clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
191 
192  clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
193  ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
194  FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
195  clk_register_clkdev(clk, "firda_mclk", NULL);
196 
197  clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
198  PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
199  clk_register_clkdev(clk, NULL, "firda");
200 
201  clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk",
202  0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
203  &_lock, &clk1);
204  clk_register_clkdev(clk, "clcd_syn_clk", NULL);
205  clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
206 
207  clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
208  ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG,
209  CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock);
210  clk_register_clkdev(clk, "clcd_mclk", NULL);
211 
212  clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
213  PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
214  clk_register_clkdev(clk, NULL, "clcd");
215 
216  /* gpt clocks */
217  clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
218  gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
219  clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
220 
221  clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
222  ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
223  GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
224  clk_register_clkdev(clk, NULL, "gpt0");
225 
226  clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
227  ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
228  GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
229  clk_register_clkdev(clk, "gpt1_mclk", NULL);
230 
231  clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
232  PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
233  clk_register_clkdev(clk, NULL, "gpt1");
234 
235  clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
236  gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
237  clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
238 
239  clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
240  ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
241  GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
242  clk_register_clkdev(clk, "gpt2_mclk", NULL);
243 
244  clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
245  PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
246  clk_register_clkdev(clk, NULL, "gpt2");
247 
248  clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
249  gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
250  clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
251 
252  clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
253  ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG,
254  GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
255  clk_register_clkdev(clk, "gpt3_mclk", NULL);
256 
257  clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
258  PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
259  clk_register_clkdev(clk, NULL, "gpt3");
260 
261  /* clock derived from pll3 clk */
262  clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
263  PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
264  clk_register_clkdev(clk, NULL, "usbh.0_clk");
265 
266  clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
267  PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
268  clk_register_clkdev(clk, NULL, "usbh.1_clk");
269 
270  clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
271  USBD_CLK_ENB, 0, &_lock);
272  clk_register_clkdev(clk, NULL, "designware_udc");
273 
274  /* clock derived from ahb clk */
275  clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
276  1);
277  clk_register_clkdev(clk, "ahbmult2_clk", NULL);
278 
279  clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
280  ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT,
281  MCTR_CLK_MASK, 0, &_lock);
282  clk_register_clkdev(clk, "ddr_clk", NULL);
283 
284  clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
285  CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
286  PCLK_RATIO_MASK, 0, &_lock);
287  clk_register_clkdev(clk, "apb_clk", NULL);
288 
289  clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
290  DMA_CLK_ENB, 0, &_lock);
291  clk_register_clkdev(clk, NULL, "fc400000.dma");
292 
293  clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
294  FSMC_CLK_ENB, 0, &_lock);
295  clk_register_clkdev(clk, NULL, "d1800000.flash");
296 
297  clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
298  GMAC_CLK_ENB, 0, &_lock);
299  clk_register_clkdev(clk, NULL, "e0800000.ethernet");
300 
301  clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
302  I2C_CLK_ENB, 0, &_lock);
303  clk_register_clkdev(clk, NULL, "d0200000.i2c");
304 
305  clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
306  JPEG_CLK_ENB, 0, &_lock);
307  clk_register_clkdev(clk, NULL, "jpeg");
308 
309  clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
310  SMI_CLK_ENB, 0, &_lock);
311  clk_register_clkdev(clk, NULL, "fc000000.flash");
312 
313  /* clock derived from apb clk */
314  clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
315  ADC_CLK_ENB, 0, &_lock);
316  clk_register_clkdev(clk, NULL, "adc");
317 
318  clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
319  clk_register_clkdev(clk, NULL, "f0100000.gpio");
320 
321  clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
322  GPIO1_CLK_ENB, 0, &_lock);
323  clk_register_clkdev(clk, NULL, "fc980000.gpio");
324 
325  clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
326  GPIO2_CLK_ENB, 0, &_lock);
327  clk_register_clkdev(clk, NULL, "d8100000.gpio");
328 
329  clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
330  SSP0_CLK_ENB, 0, &_lock);
331  clk_register_clkdev(clk, NULL, "ssp-pl022.0");
332 
333  clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
334  SSP1_CLK_ENB, 0, &_lock);
335  clk_register_clkdev(clk, NULL, "ssp-pl022.1");
336 
337  clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
338  SSP2_CLK_ENB, 0, &_lock);
339  clk_register_clkdev(clk, NULL, "ssp-pl022.2");
340 }
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