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11 #define GLOB_CTRL 0x00UL
12 #define GLOB_STAT 0x04UL
13 #define GLOB_PSIZE 0x08UL
14 #define GLOB_MSIZE 0x0cUL
15 #define GLOB_RSIZE 0x10UL
16 #define GLOB_TSIZE 0x14UL
17 #define GLOB_REG_SIZE 0x18UL
19 #define GLOB_CTRL_MMODE 0x40000000
20 #define GLOB_CTRL_BMODE 0x10000000
21 #define GLOB_CTRL_EPAR 0x00000020
22 #define GLOB_CTRL_ACNTRL 0x00000018
23 #define GLOB_CTRL_B64 0x00000004
24 #define GLOB_CTRL_B32 0x00000002
25 #define GLOB_CTRL_B16 0x00000000
26 #define GLOB_CTRL_RESET 0x00000001
28 #define GLOB_STAT_TX 0x00000008
29 #define GLOB_STAT_RX 0x00000004
30 #define GLOB_STAT_BM 0x00000002
31 #define GLOB_STAT_ER 0x00000001
33 #define GLOB_PSIZE_2048 0x00
34 #define GLOB_PSIZE_4096 0x01
35 #define GLOB_PSIZE_6144 0x10
36 #define GLOB_PSIZE_8192 0x11
42 #define GLOB_STAT_PER_QE(status, channel) (((status) >> ((channel) * 4)) & 0xf)
45 #define CREG_CTRL 0x00UL
46 #define CREG_STAT 0x04UL
47 #define CREG_RXDS 0x08UL
48 #define CREG_TXDS 0x0cUL
49 #define CREG_RIMASK 0x10UL
50 #define CREG_TIMASK 0x14UL
51 #define CREG_QMASK 0x18UL
52 #define CREG_MMASK 0x1cUL
53 #define CREG_RXWBUFPTR 0x20UL
54 #define CREG_RXRBUFPTR 0x24UL
55 #define CREG_TXWBUFPTR 0x28UL
56 #define CREG_TXRBUFPTR 0x2cUL
57 #define CREG_CCNT 0x30UL
58 #define CREG_PIPG 0x34UL
59 #define CREG_REG_SIZE 0x38UL
61 #define CREG_CTRL_RXOFF 0x00000004
62 #define CREG_CTRL_RESET 0x00000002
63 #define CREG_CTRL_TWAKEUP 0x00000001
65 #define CREG_STAT_EDEFER 0x10000000
66 #define CREG_STAT_CLOSS 0x08000000
67 #define CREG_STAT_ERETRIES 0x04000000
68 #define CREG_STAT_LCOLL 0x02000000
69 #define CREG_STAT_FUFLOW 0x01000000
70 #define CREG_STAT_JERROR 0x00800000
71 #define CREG_STAT_BERROR 0x00400000
72 #define CREG_STAT_TXIRQ 0x00200000
73 #define CREG_STAT_CCOFLOW 0x00100000
74 #define CREG_STAT_TXDERROR 0x00080000
75 #define CREG_STAT_TXLERR 0x00040000
76 #define CREG_STAT_TXPERR 0x00020000
77 #define CREG_STAT_TXSERR 0x00010000
78 #define CREG_STAT_RCCOFLOW 0x00001000
79 #define CREG_STAT_RUOFLOW 0x00000800
80 #define CREG_STAT_MCOFLOW 0x00000400
81 #define CREG_STAT_RXFOFLOW 0x00000200
82 #define CREG_STAT_RLCOLL 0x00000100
83 #define CREG_STAT_FCOFLOW 0x00000080
84 #define CREG_STAT_CECOFLOW 0x00000040
85 #define CREG_STAT_RXIRQ 0x00000020
86 #define CREG_STAT_RXDROP 0x00000010
87 #define CREG_STAT_RXSMALL 0x00000008
88 #define CREG_STAT_RXLERR 0x00000004
89 #define CREG_STAT_RXPERR 0x00000002
90 #define CREG_STAT_RXSERR 0x00000001
92 #define CREG_STAT_ERRORS (CREG_STAT_EDEFER|CREG_STAT_CLOSS|CREG_STAT_ERETRIES| \
93 CREG_STAT_LCOLL|CREG_STAT_FUFLOW|CREG_STAT_JERROR| \
94 CREG_STAT_BERROR|CREG_STAT_CCOFLOW|CREG_STAT_TXDERROR| \
95 CREG_STAT_TXLERR|CREG_STAT_TXPERR|CREG_STAT_TXSERR| \
96 CREG_STAT_RCCOFLOW|CREG_STAT_RUOFLOW|CREG_STAT_MCOFLOW| \
97 CREG_STAT_RXFOFLOW|CREG_STAT_RLCOLL|CREG_STAT_FCOFLOW| \
98 CREG_STAT_CECOFLOW|CREG_STAT_RXDROP|CREG_STAT_RXSMALL| \
99 CREG_STAT_RXLERR|CREG_STAT_RXPERR|CREG_STAT_RXSERR)
101 #define CREG_QMASK_COFLOW 0x00100000
102 #define CREG_QMASK_TXDERROR 0x00080000
103 #define CREG_QMASK_TXLERR 0x00040000
104 #define CREG_QMASK_TXPERR 0x00020000
105 #define CREG_QMASK_TXSERR 0x00010000
106 #define CREG_QMASK_RXDROP 0x00000010
107 #define CREG_QMASK_RXBERROR 0x00000008
108 #define CREG_QMASK_RXLEERR 0x00000004
109 #define CREG_QMASK_RXPERR 0x00000002
110 #define CREG_QMASK_RXSERR 0x00000001
112 #define CREG_MMASK_EDEFER 0x10000000
113 #define CREG_MMASK_CLOSS 0x08000000
114 #define CREG_MMASK_ERETRY 0x04000000
115 #define CREG_MMASK_LCOLL 0x02000000
116 #define CREG_MMASK_UFLOW 0x01000000
117 #define CREG_MMASK_JABBER 0x00800000
118 #define CREG_MMASK_BABBLE 0x00400000
119 #define CREG_MMASK_OFLOW 0x00000800
120 #define CREG_MMASK_RXCOLL 0x00000400
121 #define CREG_MMASK_RPKT 0x00000200
122 #define CREG_MMASK_MPKT 0x00000100
124 #define CREG_PIPG_TENAB 0x00000020
125 #define CREG_PIPG_MMODE 0x00000010
126 #define CREG_PIPG_WMASK 0x0000000f
129 #define MREGS_RXFIFO 0x00UL
130 #define MREGS_TXFIFO 0x01UL
131 #define MREGS_TXFCNTL 0x02UL
132 #define MREGS_TXFSTAT 0x03UL
133 #define MREGS_TXRCNT 0x04UL
134 #define MREGS_RXFCNTL 0x05UL
135 #define MREGS_RXFSTAT 0x06UL
136 #define MREGS_FFCNT 0x07UL
137 #define MREGS_IREG 0x08UL
138 #define MREGS_IMASK 0x09UL
139 #define MREGS_POLL 0x0aUL
140 #define MREGS_BCONFIG 0x0bUL
141 #define MREGS_FCONFIG 0x0cUL
142 #define MREGS_MCONFIG 0x0dUL
143 #define MREGS_PLSCONFIG 0x0eUL
144 #define MREGS_PHYCONFIG 0x0fUL
145 #define MREGS_CHIPID1 0x10UL
146 #define MREGS_CHIPID2 0x11UL
147 #define MREGS_IACONFIG 0x12UL
149 #define MREGS_FILTER 0x14UL
150 #define MREGS_ETHADDR 0x15UL
153 #define MREGS_MPCNT 0x18UL
155 #define MREGS_RPCNT 0x1aUL
156 #define MREGS_RCCNT 0x1bUL
158 #define MREGS_UTEST 0x1dUL
159 #define MREGS_RTEST1 0x1eUL
160 #define MREGS_RTEST2 0x1fUL
161 #define MREGS_REG_SIZE 0x20UL
163 #define MREGS_TXFCNTL_DRETRY 0x80
164 #define MREGS_TXFCNTL_DFCS 0x08
165 #define MREGS_TXFCNTL_AUTOPAD 0x01
167 #define MREGS_TXFSTAT_VALID 0x80
168 #define MREGS_TXFSTAT_UNDERFLOW 0x40
169 #define MREGS_TXFSTAT_LCOLL 0x20
170 #define MREGS_TXFSTAT_MRETRY 0x10
171 #define MREGS_TXFSTAT_ORETRY 0x08
172 #define MREGS_TXFSTAT_PDEFER 0x04
173 #define MREGS_TXFSTAT_CLOSS 0x02
174 #define MREGS_TXFSTAT_RERROR 0x01
176 #define MREGS_TXRCNT_EDEFER 0x80
177 #define MREGS_TXRCNT_CMASK 0x0f
179 #define MREGS_RXFCNTL_LOWLAT 0x08
180 #define MREGS_RXFCNTL_AREJECT 0x04
181 #define MREGS_RXFCNTL_AUTOSTRIP 0x01
183 #define MREGS_RXFSTAT_OVERFLOW 0x80
184 #define MREGS_RXFSTAT_LCOLL 0x40
185 #define MREGS_RXFSTAT_FERROR 0x20
186 #define MREGS_RXFSTAT_FCSERROR 0x10
187 #define MREGS_RXFSTAT_RBCNT 0x0f
189 #define MREGS_FFCNT_RX 0xf0
190 #define MREGS_FFCNT_TX 0x0f
192 #define MREGS_IREG_JABBER 0x80
193 #define MREGS_IREG_BABBLE 0x40
194 #define MREGS_IREG_COLL 0x20
195 #define MREGS_IREG_RCCO 0x10
196 #define MREGS_IREG_RPKTCO 0x08
197 #define MREGS_IREG_MPKTCO 0x04
198 #define MREGS_IREG_RXIRQ 0x02
199 #define MREGS_IREG_TXIRQ 0x01
201 #define MREGS_IMASK_BABBLE 0x40
202 #define MREGS_IMASK_COLL 0x20
203 #define MREGS_IMASK_MPKTCO 0x04
204 #define MREGS_IMASK_RXIRQ 0x02
205 #define MREGS_IMASK_TXIRQ 0x01
207 #define MREGS_POLL_TXVALID 0x80
208 #define MREGS_POLL_TDTR 0x40
209 #define MREGS_POLL_RDTR 0x20
211 #define MREGS_BCONFIG_BSWAP 0x40
212 #define MREGS_BCONFIG_4TS 0x00
213 #define MREGS_BCONFIG_16TS 0x10
214 #define MREGS_BCONFIG_64TS 0x20
215 #define MREGS_BCONFIG_112TS 0x30
216 #define MREGS_BCONFIG_RESET 0x01
218 #define MREGS_FCONFIG_TXF8 0x00
219 #define MREGS_FCONFIG_TXF32 0x80
220 #define MREGS_FCONFIG_TXF16 0x40
221 #define MREGS_FCONFIG_RXF64 0x20
222 #define MREGS_FCONFIG_RXF32 0x10
223 #define MREGS_FCONFIG_RXF16 0x00
224 #define MREGS_FCONFIG_TFWU 0x08
225 #define MREGS_FCONFIG_RFWU 0x04
226 #define MREGS_FCONFIG_TBENAB 0x02
227 #define MREGS_FCONFIG_RBENAB 0x01
229 #define MREGS_MCONFIG_PROMISC 0x80
230 #define MREGS_MCONFIG_TPDDISAB 0x40
231 #define MREGS_MCONFIG_MBAENAB 0x20
232 #define MREGS_MCONFIG_RPADISAB 0x08
233 #define MREGS_MCONFIG_RBDISAB 0x04
234 #define MREGS_MCONFIG_TXENAB 0x02
235 #define MREGS_MCONFIG_RXENAB 0x01
237 #define MREGS_PLSCONFIG_TXMS 0x08
238 #define MREGS_PLSCONFIG_GPSI 0x06
239 #define MREGS_PLSCONFIG_DAI 0x04
240 #define MREGS_PLSCONFIG_TP 0x02
241 #define MREGS_PLSCONFIG_AUI 0x00
242 #define MREGS_PLSCONFIG_IOENAB 0x01
244 #define MREGS_PHYCONFIG_LSTAT 0x80
245 #define MREGS_PHYCONFIG_LTESTDIS 0x40
246 #define MREGS_PHYCONFIG_RXPOLARITY 0x20
247 #define MREGS_PHYCONFIG_APCDISAB 0x10
248 #define MREGS_PHYCONFIG_LTENAB 0x08
249 #define MREGS_PHYCONFIG_AUTO 0x04
250 #define MREGS_PHYCONFIG_RWU 0x02
251 #define MREGS_PHYCONFIG_AW 0x01
253 #define MREGS_IACONFIG_ACHNGE 0x80
254 #define MREGS_IACONFIG_PARESET 0x04
255 #define MREGS_IACONFIG_LARESET 0x02
257 #define MREGS_UTEST_RTRENAB 0x80
258 #define MREGS_UTEST_RTRDISAB 0x40
259 #define MREGS_UTEST_RPACCEPT 0x20
260 #define MREGS_UTEST_FCOLL 0x10
261 #define MREGS_UTEST_FCSENAB 0x08
262 #define MREGS_UTEST_INTLOOPM 0x06
263 #define MREGS_UTEST_INTLOOP 0x04
264 #define MREGS_UTEST_EXTLOOP 0x02
265 #define MREGS_UTEST_NOLOOP 0x00
272 #define RXD_OWN 0x80000000
273 #define RXD_UPDATE 0x10000000
274 #define RXD_LENGTH 0x000007ff
281 #define TXD_OWN 0x80000000
282 #define TXD_SOP 0x40000000
283 #define TXD_EOP 0x20000000
284 #define TXD_UPDATE 0x10000000
285 #define TXD_LENGTH 0x000007ff
287 #define TX_RING_MAXSIZE 256
288 #define RX_RING_MAXSIZE 256
290 #define TX_RING_SIZE 16
291 #define RX_RING_SIZE 16
293 #define NEXT_RX(num) (((num) + 1) & (RX_RING_MAXSIZE - 1))
294 #define NEXT_TX(num) (((num) + 1) & (TX_RING_MAXSIZE - 1))
295 #define PREV_RX(num) (((num) - 1) & (RX_RING_MAXSIZE - 1))
296 #define PREV_TX(num) (((num) - 1) & (TX_RING_MAXSIZE - 1))
298 #define TX_BUFFS_AVAIL(qp) \
299 (((qp)->tx_old <= (qp)->tx_new) ? \
300 (qp)->tx_old + (TX_RING_SIZE - 1) - (qp)->tx_new : \
301 (qp)->tx_old - (qp)->tx_new - 1)
308 #define qib_offset(mem, elem) \
309 ((__u32)((unsigned long)(&(((struct qe_init_block *)0)->mem[elem]))))
321 #define PKT_BUF_SZ 1664
322 #define RXD_PKT_SZ 1664
330 #define qebuf_offset(mem, elem) \
331 ((__u32)((unsigned long)(&(((struct sunqe_buffers *)0)->mem[elem][0]))))