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23 #ifndef __TEGRA20_DAS_H__
24 #define __TEGRA20_DAS_H__
27 #define TEGRA20_DAS_DAP_CTRL_SEL 0x00
28 #define TEGRA20_DAS_DAP_CTRL_SEL_COUNT 5
29 #define TEGRA20_DAS_DAP_CTRL_SEL_STRIDE 4
30 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P 31
31 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S 1
32 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P 30
33 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S 1
34 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P 29
35 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S 1
36 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P 0
37 #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S 5
40 #define TEGRA20_DAS_DAP_SEL_DAC1 0
41 #define TEGRA20_DAS_DAP_SEL_DAC2 1
42 #define TEGRA20_DAS_DAP_SEL_DAC3 2
43 #define TEGRA20_DAS_DAP_SEL_DAP1 16
44 #define TEGRA20_DAS_DAP_SEL_DAP2 17
45 #define TEGRA20_DAS_DAP_SEL_DAP3 18
46 #define TEGRA20_DAS_DAP_SEL_DAP4 19
47 #define TEGRA20_DAS_DAP_SEL_DAP5 20
50 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL 0x40
51 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT 3
52 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE 4
53 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P 28
54 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S 4
55 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P 24
56 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S 4
57 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P 0
58 #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S 4
66 #define TEGRA20_DAS_DAC_SEL_DAP1 0
67 #define TEGRA20_DAS_DAC_SEL_DAP2 1
68 #define TEGRA20_DAS_DAC_SEL_DAP3 2
69 #define TEGRA20_DAS_DAC_SEL_DAP4 3
70 #define TEGRA20_DAS_DAC_SEL_DAP5 4
76 #define TEGRA20_DAS_DAP_ID_1 0
77 #define TEGRA20_DAS_DAP_ID_2 1
78 #define TEGRA20_DAS_DAP_ID_3 2
79 #define TEGRA20_DAS_DAP_ID_4 3
80 #define TEGRA20_DAS_DAP_ID_5 4
82 #define TEGRA20_DAS_DAC_ID_1 0
83 #define TEGRA20_DAS_DAC_ID_2 1
84 #define TEGRA20_DAS_DAC_ID_3 2
123 int master,
int sdata1rx,