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17 #ifndef __ARCH_TRIO_DEF_H__
18 #define __ARCH_TRIO_DEF_H__
19 #define TRIO_CFG_REGION_ADDR__REG_SHIFT 0
20 #define TRIO_CFG_REGION_ADDR__INTFC_SHIFT 16
21 #define TRIO_CFG_REGION_ADDR__INTFC_VAL_TRIO 0x0
22 #define TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE 0x1
23 #define TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD 0x2
24 #define TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED 0x3
25 #define TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT 18
26 #define TRIO_CFG_REGION_ADDR__PROT_SHIFT 20
27 #define TRIO_PIO_REGIONS_ADDR__REGION_SHIFT 32
28 #define TRIO_MAP_MEM_REG_INT0 0x1000000000
29 #define TRIO_MAP_MEM_REG_INT1 0x1000000008
30 #define TRIO_MAP_MEM_REG_INT2 0x1000000010
31 #define TRIO_MAP_MEM_REG_INT3 0x1000000018
32 #define TRIO_MAP_MEM_REG_INT4 0x1000000020
33 #define TRIO_MAP_MEM_REG_INT5 0x1000000028
34 #define TRIO_MAP_MEM_REG_INT6 0x1000000030
35 #define TRIO_MAP_MEM_REG_INT7 0x1000000038
36 #define TRIO_MAP_MEM_LIM__ADDR_SHIFT 12
37 #define TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_UNORDERED 0x0
38 #define TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_STRICT 0x1
39 #define TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_REL_ORD 0x2
40 #define TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT 30