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u300-regs.h
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1 /*
2  *
3  * arch/arm/mach-u300/include/mach/u300-regs.h
4  *
5  *
6  * Copyright (C) 2006-2009 ST-Ericsson AB
7  * License terms: GNU General Public License (GPL) version 2
8  * Basic register address definitions in physical memory and
9  * some block definitions for core devices like the timer.
10  * Author: Linus Walleij <[email protected]>
11  */
12 
13 #ifndef __MACH_U300_REGS_H
14 #define __MACH_U300_REGS_H
15 
16 /*
17  * These are the large blocks of memory allocated for I/O.
18  * the defines are used for setting up the I/O memory mapping.
19  */
20 
21 /* NAND Flash CS0 */
22 #define U300_NAND_CS0_PHYS_BASE 0x80000000
23 
24 /* NFIF */
25 #define U300_NAND_IF_PHYS_BASE 0x9f800000
26 
27 /* ALE, CLE offset for FSMC NAND */
28 #define PLAT_NAND_CLE (1 << 16)
29 #define PLAT_NAND_ALE (1 << 17)
30 
31 /* AHB Peripherals */
32 #define U300_AHB_PER_PHYS_BASE 0xa0000000
33 #define U300_AHB_PER_VIRT_BASE 0xff010000
34 
35 /* FAST Peripherals */
36 #define U300_FAST_PER_PHYS_BASE 0xc0000000
37 #define U300_FAST_PER_VIRT_BASE 0xff020000
38 
39 /* SLOW Peripherals */
40 #define U300_SLOW_PER_PHYS_BASE 0xc0010000
41 #define U300_SLOW_PER_VIRT_BASE 0xff000000
42 
43 /* Boot ROM */
44 #define U300_BOOTROM_PHYS_BASE 0xffff0000
45 #define U300_BOOTROM_VIRT_BASE 0xffff0000
46 
47 /* SEMI config base */
48 #define U300_SEMI_CONFIG_BASE 0x2FFE0000
49 
50 /*
51  * AHB peripherals
52  */
53 
54 /* AHB Peripherals Bridge Controller */
55 #define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
56 
57 /* Vectored Interrupt Controller 0, servicing 32 interrupts */
58 #define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
59 #define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
60 
61 /* Vectored Interrupt Controller 1, servicing 32 interrupts */
62 #define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
63 #define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
64 
65 /* Memory Stick Pro (MSPRO) controller */
66 #define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
67 
68 /* EMIF Configuration Area */
69 #define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
70 
71 
72 /*
73  * FAST peripherals
74  */
75 
76 /* FAST bridge control */
77 #define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
78 
79 /* MMC/SD controller */
80 #define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
81 
82 /* PCM I2S0 controller */
83 #define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
84 
85 /* PCM I2S1 controller */
86 #define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
87 
88 /* I2C0 controller */
89 #define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
90 
91 /* I2C1 controller */
92 #define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
93 
94 /* SPI controller */
95 #define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
96 
97 /* Fast UART1 on U335 only */
98 #define U300_UART1_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
99 
100 /*
101  * SLOW peripherals
102  */
103 
104 /* SLOW bridge control */
105 #define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE)
106 
107 /* SYSCON */
108 #define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
109 #define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
110 
111 /* Watchdog */
112 #define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
113 
114 /* UART0 */
115 #define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
116 
117 /* APP side special timer */
118 #define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
119 #define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
120 
121 /* Keypad */
122 #define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
123 
124 /* GPIO */
125 #define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
126 
127 /* RTC */
128 #define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
129 
130 /* Bus tracer */
131 #define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
132 
133 /* Event handler (hardware queue) */
134 #define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
135 
136 /* Genric Timer */
137 #define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
138 
139 /* PPM */
140 #define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
141 
142 
143 /*
144  * REST peripherals
145  */
146 
147 /* ISP (image signal processor) */
148 #define U300_ISP_BASE (0xA0008000)
149 
150 /* DMA Controller base */
151 #define U300_DMAC_BASE (0xC0020000)
152 
153 /* MSL Base */
154 #define U300_MSL_BASE (0xc0022000)
155 
156 /* APEX Base */
157 #define U300_APEX_BASE (0xc0030000)
158 
159 /* Video Encoder Base */
160 #define U300_VIDEOENC_BASE (0xc0080000)
161 
162 /* XGAM Base */
163 #define U300_XGAM_BASE (0xd0000000)
164 
165 #endif