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mii.h
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1 /*
2  * linux/mii.h: definitions for MII-compatible transceivers
3  * Originally drivers/net/sunhme.h.
4  *
5  * Copyright (C) 1996, 1999, 2001 David S. Miller ([email protected])
6  */
7 
8 #ifndef _UAPI__LINUX_MII_H__
9 #define _UAPI__LINUX_MII_H__
10 
11 #include <linux/types.h>
12 #include <linux/ethtool.h>
13 
14 /* Generic MII registers. */
15 #define MII_BMCR 0x00 /* Basic mode control register */
16 #define MII_BMSR 0x01 /* Basic mode status register */
17 #define MII_PHYSID1 0x02 /* PHYS ID 1 */
18 #define MII_PHYSID2 0x03 /* PHYS ID 2 */
19 #define MII_ADVERTISE 0x04 /* Advertisement control reg */
20 #define MII_LPA 0x05 /* Link partner ability reg */
21 #define MII_EXPANSION 0x06 /* Expansion register */
22 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
23 #define MII_STAT1000 0x0a /* 1000BASE-T status */
24 #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
25 #define MII_MMD_DATA 0x0e /* MMD Access Data Register */
26 #define MII_ESTATUS 0x0f /* Extended Status */
27 #define MII_DCOUNTER 0x12 /* Disconnect counter */
28 #define MII_FCSCOUNTER 0x13 /* False carrier counter */
29 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
30 #define MII_RERRCOUNTER 0x15 /* Receive error counter */
31 #define MII_SREVISION 0x16 /* Silicon revision */
32 #define MII_RESV1 0x17 /* Reserved... */
33 #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
34 #define MII_PHYADDR 0x19 /* PHY address */
35 #define MII_RESV2 0x1a /* Reserved... */
36 #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
37 #define MII_NCONFIG 0x1c /* Network interface config */
38 
39 /* Basic mode control register. */
40 #define BMCR_RESV 0x003f /* Unused... */
41 #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
42 #define BMCR_CTST 0x0080 /* Collision test */
43 #define BMCR_FULLDPLX 0x0100 /* Full duplex */
44 #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
45 #define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */
46 #define BMCR_PDOWN 0x0800 /* Enable low power state */
47 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
48 #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
49 #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
50 #define BMCR_RESET 0x8000 /* Reset to default state */
51 
52 /* Basic mode status register. */
53 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
54 #define BMSR_JCD 0x0002 /* Jabber detected */
55 #define BMSR_LSTATUS 0x0004 /* Link status */
56 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
57 #define BMSR_RFAULT 0x0010 /* Remote fault detected */
58 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
59 #define BMSR_RESV 0x00c0 /* Unused... */
60 #define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
61 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
62 #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
63 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
64 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
65 #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
66 #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
67 #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
68 
69 /* Advertisement control register. */
70 #define ADVERTISE_SLCT 0x001f /* Selector bits */
71 #define ADVERTISE_CSMA 0x0001 /* Only selector supported */
72 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
73 #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
74 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
75 #define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
76 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
77 #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
78 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
79 #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
80 #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
81 #define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
82 #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
83 #define ADVERTISE_RESV 0x1000 /* Unused... */
84 #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
85 #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
86 #define ADVERTISE_NPAGE 0x8000 /* Next page bit */
87 
88 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
89  ADVERTISE_CSMA)
90 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
91  ADVERTISE_100HALF | ADVERTISE_100FULL)
92 
93 /* Link partner ability register. */
94 #define LPA_SLCT 0x001f /* Same as advertise selector */
95 #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
96 #define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
97 #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
98 #define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
99 #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
100 #define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
101 #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
102 #define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
103 #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
104 #define LPA_PAUSE_CAP 0x0400 /* Can pause */
105 #define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
106 #define LPA_RESV 0x1000 /* Unused... */
107 #define LPA_RFAULT 0x2000 /* Link partner faulted */
108 #define LPA_LPACK 0x4000 /* Link partner acked us */
109 #define LPA_NPAGE 0x8000 /* Next page bit */
110 
111 #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
112 #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
113 
114 /* Expansion register for auto-negotiation. */
115 #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
116 #define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
117 #define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
118 #define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
119 #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
120 #define EXPANSION_RESV 0xffe0 /* Unused... */
121 
122 #define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
123 #define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
124 
125 /* N-way test register. */
126 #define NWAYTEST_RESV1 0x00ff /* Unused... */
127 #define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
128 #define NWAYTEST_RESV2 0xfe00 /* Unused... */
129 
130 /* 1000BASE-T Control register */
131 #define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
132 #define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
133 #define CTL1000_AS_MASTER 0x0800
134 #define CTL1000_ENABLE_MASTER 0x1000
135 
136 /* 1000BASE-T Status register */
137 #define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
138 #define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
139 #define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
140 #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
141 
142 /* Flow control flags */
143 #define FLOW_CTRL_TX 0x01
144 #define FLOW_CTRL_RX 0x02
145 
146 /* MMD Access Control register fields */
147 #define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/
148 #define MII_MMD_CTRL_ADDR 0x0000 /* Address */
149 #define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */
150 #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
151 #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */
152 
153 /* This structure is used in all SIOCxMIIxxx ioctl calls */
154 struct mii_ioctl_data {
155  __u16 phy_id;
156  __u16 reg_num;
157  __u16 val_in;
158  __u16 val_out;
159 };
160 
161 #endif /* _UAPI__LINUX_MII_H__ */
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