Go to the documentation of this file. 1 #ifndef __MACH_URQUELL_H
2 #define __MACH_URQUELL_H
23 #define NOR_FLASH_ADDR 0x00000000
24 #define NOR_FLASH_SIZE 0x04000000
26 #define CS1_BASE 0x05000000
27 #define CS5_BASE 0x15000000
28 #define FPGA_BASE CS1_BASE
30 #define BOARDREG(ofs) (FPGA_BASE + ofs##_OFS)
31 #define UBOARDREG(ofs) (0xa0000000 + FPGA_BASE + ofs##_OFS)
33 #define SRSTR_OFS 0x0000
34 #define BDMR_OFS 0x0010
35 #define IRL0SR_OFS 0x0020
36 #define IRL0MSKR_OFS 0x0030
37 #define IRL1SR_OFS 0x0040
38 #define IRL1MSKR_OFS 0x0050
39 #define IRL2SR_OFS 0x0060
40 #define IRL2MSKR_OFS 0x0070
41 #define IRL3SR_OFS 0x0080
42 #define IRL3MSKR_OFS 0x0090
43 #define SOFTINTR_OFS 0x0120
44 #define SLEDR_OFS 0x0130
45 #define MAPSCIFSWR_OFS 0x0140
46 #define FPVERR_OFS 0x0150
47 #define FPDATER_OFS 0x0160
48 #define FPYEARR_OFS 0x0170
49 #define TCLKCR_OFS 0x0180
50 #define DIPSWMR_OFS 0x1000
51 #define FPODR_OFS 0x1010
52 #define ATACNR_OFS 0x1020
53 #define FPINDR_OFS 0x1030
54 #define MDSWMR_OFS 0x1040
55 #define DDR3BUPCR_OFS 0x1050
56 #define SSICODECCR_OFS 0x1060
57 #define PCIESLOTSR_OFS 0x1070
58 #define ETHERPORTSR_OFS 0x1080
59 #define LATCHCR_OFS 0x3000
60 #define LATCUAR_OFS 0x3010
61 #define LATCLAR_OFS 0x3012
62 #define LATCLUDR_OFS 0x3024
63 #define LATCLLDR_OFS 0x3026
65 #define CHARLED_OFS 0x2000