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v4l2-dv-timings.h
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1 /*
2  * V4L2 DV timings header.
3  *
4  * Copyright (C) 2012 Hans Verkuil <[email protected]>
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * version 2 as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13  * General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18  * 02110-1301 USA
19  */
20 
21 #ifndef _V4L2_DV_TIMINGS_H
22 #define _V4L2_DV_TIMINGS_H
23 
24 #if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6))
25 /* Sadly gcc versions older than 4.6 have a bug in how they initialize
26  anonymous unions where they require additional curly brackets.
27  This violates the C1x standard. This workaround adds the curly brackets
28  if needed. */
29 #define V4L2_INIT_BT_TIMINGS(_width, args...) \
30  { .bt = { _width , ## args } }
31 #else
32 #define V4L2_INIT_BT_TIMINGS(_width, args...) \
33  .bt = { _width , ## args }
34 #endif
35 
36 /* CEA-861-E timings (i.e. standard HDTV timings) */
37 
38 #define V4L2_DV_BT_CEA_640X480P59_94 { \
39  .type = V4L2_DV_BT_656_1120, \
40  V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
41  25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \
42  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, 0) \
43 }
44 
45 #define V4L2_DV_BT_CEA_720X480P59_94 { \
46  .type = V4L2_DV_BT_656_1120, \
47  V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
48  27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
49  V4L2_DV_BT_STD_CEA861, 0) \
50 }
51 
52 #define V4L2_DV_BT_CEA_720X576P50 { \
53  .type = V4L2_DV_BT_656_1120, \
54  V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
55  27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
56  V4L2_DV_BT_STD_CEA861, 0) \
57 }
58 
59 #define V4L2_DV_BT_CEA_1280X720P24 { \
60  .type = V4L2_DV_BT_656_1120, \
61  V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
62  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
63  59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
64  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
65  V4L2_DV_FL_CAN_REDUCE_FPS) \
66 }
67 
68 #define V4L2_DV_BT_CEA_1280X720P25 { \
69  .type = V4L2_DV_BT_656_1120, \
70  V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
71  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
72  74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
73  V4L2_DV_BT_STD_CEA861, 0) \
74 }
75 
76 #define V4L2_DV_BT_CEA_1280X720P30 { \
77  .type = V4L2_DV_BT_656_1120, \
78  V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
79  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
80  74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
81  V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
82 }
83 
84 #define V4L2_DV_BT_CEA_1280X720P50 { \
85  .type = V4L2_DV_BT_656_1120, \
86  V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
87  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
88  74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
89  V4L2_DV_BT_STD_CEA861, 0) \
90 }
91 
92 #define V4L2_DV_BT_CEA_1280X720P60 { \
93  .type = V4L2_DV_BT_656_1120, \
94  V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
95  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
96  74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
97  V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
98 }
99 
100 #define V4L2_DV_BT_CEA_1920X1080P24 { \
101  .type = V4L2_DV_BT_656_1120, \
102  V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
103  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
104  74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
105  V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
106 }
107 
108 #define V4L2_DV_BT_CEA_1920X1080P25 { \
109  .type = V4L2_DV_BT_656_1120, \
110  V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
111  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
112  74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
113  V4L2_DV_BT_STD_CEA861, 0) \
114 }
115 
116 #define V4L2_DV_BT_CEA_1920X1080P30 { \
117  .type = V4L2_DV_BT_656_1120, \
118  V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
119  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
120  74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
121  V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
122 }
123 
124 #define V4L2_DV_BT_CEA_1920X1080I50 { \
125  .type = V4L2_DV_BT_656_1120, \
126  V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
127  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
128  74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
129  V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
130 }
131 
132 #define V4L2_DV_BT_CEA_1920X1080P50 { \
133  .type = V4L2_DV_BT_656_1120, \
134  V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
135  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
136  148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
137  V4L2_DV_BT_STD_CEA861, 0) \
138 }
139 
140 #define V4L2_DV_BT_CEA_1920X1080I60 { \
141  .type = V4L2_DV_BT_656_1120, \
142  V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
143  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
144  74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
145  V4L2_DV_BT_STD_CEA861, \
146  V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE) \
147 }
148 
149 #define V4L2_DV_BT_CEA_1920X1080P60 { \
150  .type = V4L2_DV_BT_656_1120, \
151  V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
152  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
153  148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
154  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
155  V4L2_DV_FL_CAN_REDUCE_FPS) \
156 }
157 
158 
159 /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */
160 
161 #define V4L2_DV_BT_DMT_640X350P85 { \
162  .type = V4L2_DV_BT_656_1120, \
163  V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
164  31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \
165  V4L2_DV_BT_STD_DMT, 0) \
166 }
167 
168 #define V4L2_DV_BT_DMT_640X400P85 { \
169  .type = V4L2_DV_BT_656_1120, \
170  V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
171  31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \
172  V4L2_DV_BT_STD_DMT, 0) \
173 }
174 
175 #define V4L2_DV_BT_DMT_720X400P85 { \
176  .type = V4L2_DV_BT_656_1120, \
177  V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
178  35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \
179  V4L2_DV_BT_STD_DMT, 0) \
180 }
181 
182 /* VGA resolutions */
183 #define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94
184 
185 #define V4L2_DV_BT_DMT_640X480P72 { \
186  .type = V4L2_DV_BT_656_1120, \
187  V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
188  31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \
189  V4L2_DV_BT_STD_DMT, 0) \
190 }
191 
192 #define V4L2_DV_BT_DMT_640X480P75 { \
193  .type = V4L2_DV_BT_656_1120, \
194  V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
195  31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \
196  V4L2_DV_BT_STD_DMT, 0) \
197 }
198 
199 #define V4L2_DV_BT_DMT_640X480P85 { \
200  .type = V4L2_DV_BT_656_1120, \
201  V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
202  36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \
203  V4L2_DV_BT_STD_DMT, 0) \
204 }
205 
206 /* SVGA resolutions */
207 #define V4L2_DV_BT_DMT_800X600P56 { \
208  .type = V4L2_DV_BT_656_1120, \
209  V4L2_INIT_BT_TIMINGS(800, 600, 0, \
210  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
211  36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \
212  V4L2_DV_BT_STD_DMT, 0) \
213 }
214 
215 #define V4L2_DV_BT_DMT_800X600P60 { \
216  .type = V4L2_DV_BT_656_1120, \
217  V4L2_INIT_BT_TIMINGS(800, 600, 0, \
218  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
219  40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \
220  V4L2_DV_BT_STD_DMT, 0) \
221 }
222 
223 #define V4L2_DV_BT_DMT_800X600P72 { \
224  .type = V4L2_DV_BT_656_1120, \
225  V4L2_INIT_BT_TIMINGS(800, 600, 0, \
226  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
227  50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \
228  V4L2_DV_BT_STD_DMT, 0) \
229 }
230 
231 #define V4L2_DV_BT_DMT_800X600P75 { \
232  .type = V4L2_DV_BT_656_1120, \
233  V4L2_INIT_BT_TIMINGS(800, 600, 0, \
234  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
235  49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \
236  V4L2_DV_BT_STD_DMT, 0) \
237 }
238 
239 #define V4L2_DV_BT_DMT_800X600P85 { \
240  .type = V4L2_DV_BT_656_1120, \
241  V4L2_INIT_BT_TIMINGS(800, 600, 0, \
242  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
243  56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \
244  V4L2_DV_BT_STD_DMT, 0) \
245 }
246 
247 #define V4L2_DV_BT_DMT_800X600P120_RB { \
248  .type = V4L2_DV_BT_656_1120, \
249  V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \
250  73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \
251  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
252  V4L2_DV_FL_REDUCED_BLANKING) \
253 }
254 
255 #define V4L2_DV_BT_DMT_848X480P60 { \
256  .type = V4L2_DV_BT_656_1120, \
257  V4L2_INIT_BT_TIMINGS(848, 480, 0, \
258  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
259  33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \
260  V4L2_DV_BT_STD_DMT, 0) \
261 }
262 
263 #define V4L2_DV_BT_DMT_1024X768I43 { \
264  .type = V4L2_DV_BT_656_1120, \
265  V4L2_INIT_BT_TIMINGS(1024, 768, 1, \
266  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
267  44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \
268  V4L2_DV_BT_STD_DMT, 0) \
269 }
270 
271 /* XGA resolutions */
272 #define V4L2_DV_BT_DMT_1024X768P60 { \
273  .type = V4L2_DV_BT_656_1120, \
274  V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
275  65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \
276  V4L2_DV_BT_STD_DMT, 0) \
277 }
278 
279 #define V4L2_DV_BT_DMT_1024X768P70 { \
280  .type = V4L2_DV_BT_656_1120, \
281  V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
282  75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \
283  V4L2_DV_BT_STD_DMT, 0) \
284 }
285 
286 #define V4L2_DV_BT_DMT_1024X768P75 { \
287  .type = V4L2_DV_BT_656_1120, \
288  V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
289  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
290  78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \
291  V4L2_DV_BT_STD_DMT, 0) \
292 }
293 
294 #define V4L2_DV_BT_DMT_1024X768P85 { \
295  .type = V4L2_DV_BT_656_1120, \
296  V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
297  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
298  94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \
299  V4L2_DV_BT_STD_DMT, 0) \
300 }
301 
302 #define V4L2_DV_BT_DMT_1024X768P120_RB { \
303  .type = V4L2_DV_BT_656_1120, \
304  V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \
305  115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \
306  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
307  V4L2_DV_FL_REDUCED_BLANKING) \
308 }
309 
310 /* XGA+ resolution */
311 #define V4L2_DV_BT_DMT_1152X864P75 { \
312  .type = V4L2_DV_BT_656_1120, \
313  V4L2_INIT_BT_TIMINGS(1152, 864, 0, \
314  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
315  108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \
316  V4L2_DV_BT_STD_DMT, 0) \
317 }
318 
319 #define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60
320 
321 /* WXGA resolutions */
322 #define V4L2_DV_BT_DMT_1280X768P60_RB { \
323  .type = V4L2_DV_BT_656_1120, \
324  V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
325  68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \
326  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
327  V4L2_DV_FL_REDUCED_BLANKING) \
328 }
329 
330 #define V4L2_DV_BT_DMT_1280X768P60 { \
331  .type = V4L2_DV_BT_656_1120, \
332  V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
333  79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \
334  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
335 }
336 
337 #define V4L2_DV_BT_DMT_1280X768P75 { \
338  .type = V4L2_DV_BT_656_1120, \
339  V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
340  102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \
341  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
342 }
343 
344 #define V4L2_DV_BT_DMT_1280X768P85 { \
345  .type = V4L2_DV_BT_656_1120, \
346  V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
347  117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \
348  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
349 }
350 
351 #define V4L2_DV_BT_DMT_1280X768P120_RB { \
352  .type = V4L2_DV_BT_656_1120, \
353  V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
354  140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \
355  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
356  V4L2_DV_FL_REDUCED_BLANKING) \
357 }
358 
359 #define V4L2_DV_BT_DMT_1280X800P60_RB { \
360  .type = V4L2_DV_BT_656_1120, \
361  V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
362  71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \
363  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
364  V4L2_DV_FL_REDUCED_BLANKING) \
365 }
366 
367 #define V4L2_DV_BT_DMT_1280X800P60 { \
368  .type = V4L2_DV_BT_656_1120, \
369  V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
370  83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \
371  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
372 }
373 
374 #define V4L2_DV_BT_DMT_1280X800P75 { \
375  .type = V4L2_DV_BT_656_1120, \
376  V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
377  106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \
378  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
379 }
380 
381 #define V4L2_DV_BT_DMT_1280X800P85 { \
382  .type = V4L2_DV_BT_656_1120, \
383  V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
384  122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \
385  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
386 }
387 
388 #define V4L2_DV_BT_DMT_1280X800P120_RB { \
389  .type = V4L2_DV_BT_656_1120, \
390  V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
391  146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \
392  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
393  V4L2_DV_FL_REDUCED_BLANKING) \
394 }
395 
396 #define V4L2_DV_BT_DMT_1280X960P60 { \
397  .type = V4L2_DV_BT_656_1120, \
398  V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
399  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
400  108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \
401  V4L2_DV_BT_STD_DMT, 0) \
402 }
403 
404 #define V4L2_DV_BT_DMT_1280X960P85 { \
405  .type = V4L2_DV_BT_656_1120, \
406  V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
407  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
408  148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \
409  V4L2_DV_BT_STD_DMT, 0) \
410 }
411 
412 #define V4L2_DV_BT_DMT_1280X960P120_RB { \
413  .type = V4L2_DV_BT_656_1120, \
414  V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
415  175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \
416  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
417  V4L2_DV_FL_REDUCED_BLANKING) \
418 }
419 
420 /* SXGA resolutions */
421 #define V4L2_DV_BT_DMT_1280X1024P60 { \
422  .type = V4L2_DV_BT_656_1120, \
423  V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
424  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
425  108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \
426  V4L2_DV_BT_STD_DMT, 0) \
427 }
428 
429 #define V4L2_DV_BT_DMT_1280X1024P75 { \
430  .type = V4L2_DV_BT_656_1120, \
431  V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
432  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
433  135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \
434  V4L2_DV_BT_STD_DMT, 0) \
435 }
436 
437 #define V4L2_DV_BT_DMT_1280X1024P85 { \
438  .type = V4L2_DV_BT_656_1120, \
439  V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
440  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
441  157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \
442  V4L2_DV_BT_STD_DMT, 0) \
443 }
444 
445 #define V4L2_DV_BT_DMT_1280X1024P120_RB { \
446  .type = V4L2_DV_BT_656_1120, \
447  V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \
448  187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \
449  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
450  V4L2_DV_FL_REDUCED_BLANKING) \
451 }
452 
453 #define V4L2_DV_BT_DMT_1360X768P60 { \
454  .type = V4L2_DV_BT_656_1120, \
455  V4L2_INIT_BT_TIMINGS(1360, 768, 0, \
456  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
457  85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \
458  V4L2_DV_BT_STD_DMT, 0) \
459 }
460 
461 #define V4L2_DV_BT_DMT_1360X768P120_RB { \
462  .type = V4L2_DV_BT_656_1120, \
463  V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \
464  148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \
465  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
466  V4L2_DV_FL_REDUCED_BLANKING) \
467 }
468 
469 #define V4L2_DV_BT_DMT_1366X768P60 { \
470  .type = V4L2_DV_BT_656_1120, \
471  V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
472  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
473  85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \
474  V4L2_DV_BT_STD_DMT, 0) \
475 }
476 
477 #define V4L2_DV_BT_DMT_1366X768P60_RB { \
478  .type = V4L2_DV_BT_656_1120, \
479  V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
480  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
481  72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \
482  V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
483 }
484 
485 /* SXGA+ resolutions */
486 #define V4L2_DV_BT_DMT_1400X1050P60_RB { \
487  .type = V4L2_DV_BT_656_1120, \
488  V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
489  101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \
490  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
491  V4L2_DV_FL_REDUCED_BLANKING) \
492 }
493 
494 #define V4L2_DV_BT_DMT_1400X1050P60 { \
495  .type = V4L2_DV_BT_656_1120, \
496  V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
497  121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \
498  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
499 }
500 
501 #define V4L2_DV_BT_DMT_1400X1050P75 { \
502  .type = V4L2_DV_BT_656_1120, \
503  V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
504  156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \
505  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
506 }
507 
508 #define V4L2_DV_BT_DMT_1400X1050P85 { \
509  .type = V4L2_DV_BT_656_1120, \
510  V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
511  179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \
512  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
513 }
514 
515 #define V4L2_DV_BT_DMT_1400X1050P120_RB { \
516  .type = V4L2_DV_BT_656_1120, \
517  V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
518  208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \
519  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
520  V4L2_DV_FL_REDUCED_BLANKING) \
521 }
522 
523 /* WXGA+ resolutions */
524 #define V4L2_DV_BT_DMT_1440X900P60_RB { \
525  .type = V4L2_DV_BT_656_1120, \
526  V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
527  88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \
528  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
529  V4L2_DV_FL_REDUCED_BLANKING) \
530 }
531 
532 #define V4L2_DV_BT_DMT_1440X900P60 { \
533  .type = V4L2_DV_BT_656_1120, \
534  V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
535  106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \
536  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
537 }
538 
539 #define V4L2_DV_BT_DMT_1440X900P75 { \
540  .type = V4L2_DV_BT_656_1120, \
541  V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
542  136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \
543  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
544 }
545 
546 #define V4L2_DV_BT_DMT_1440X900P85 { \
547  .type = V4L2_DV_BT_656_1120, \
548  V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
549  157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \
550  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
551 }
552 
553 #define V4L2_DV_BT_DMT_1440X900P120_RB { \
554  .type = V4L2_DV_BT_656_1120, \
555  V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
556  182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \
557  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
558  V4L2_DV_FL_REDUCED_BLANKING) \
559 }
560 
561 #define V4L2_DV_BT_DMT_1600X900P60_RB { \
562  .type = V4L2_DV_BT_656_1120, \
563  V4L2_INIT_BT_TIMINGS(1600, 900, 0, \
564  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
565  108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \
566  V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
567 }
568 
569 /* UXGA resolutions */
570 #define V4L2_DV_BT_DMT_1600X1200P60 { \
571  .type = V4L2_DV_BT_656_1120, \
572  V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
573  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
574  162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
575  V4L2_DV_BT_STD_DMT, 0) \
576 }
577 
578 #define V4L2_DV_BT_DMT_1600X1200P65 { \
579  .type = V4L2_DV_BT_656_1120, \
580  V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
581  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
582  175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
583  V4L2_DV_BT_STD_DMT, 0) \
584 }
585 
586 #define V4L2_DV_BT_DMT_1600X1200P70 { \
587  .type = V4L2_DV_BT_656_1120, \
588  V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
589  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
590  189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
591  V4L2_DV_BT_STD_DMT, 0) \
592 }
593 
594 #define V4L2_DV_BT_DMT_1600X1200P75 { \
595  .type = V4L2_DV_BT_656_1120, \
596  V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
597  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
598  202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
599  V4L2_DV_BT_STD_DMT, 0) \
600 }
601 
602 #define V4L2_DV_BT_DMT_1600X1200P85 { \
603  .type = V4L2_DV_BT_656_1120, \
604  V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
605  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
606  229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
607  V4L2_DV_BT_STD_DMT, 0) \
608 }
609 
610 #define V4L2_DV_BT_DMT_1600X1200P120_RB { \
611  .type = V4L2_DV_BT_656_1120, \
612  V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
613  268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \
614  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
615  V4L2_DV_FL_REDUCED_BLANKING) \
616 }
617 
618 /* WSXGA+ resolutions */
619 #define V4L2_DV_BT_DMT_1680X1050P60_RB { \
620  .type = V4L2_DV_BT_656_1120, \
621  V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
622  119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \
623  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
624  V4L2_DV_FL_REDUCED_BLANKING) \
625 }
626 
627 #define V4L2_DV_BT_DMT_1680X1050P60 { \
628  .type = V4L2_DV_BT_656_1120, \
629  V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
630  146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \
631  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
632 }
633 
634 #define V4L2_DV_BT_DMT_1680X1050P75 { \
635  .type = V4L2_DV_BT_656_1120, \
636  V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
637  187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \
638  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
639 }
640 
641 #define V4L2_DV_BT_DMT_1680X1050P85 { \
642  .type = V4L2_DV_BT_656_1120, \
643  V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
644  214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \
645  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
646 }
647 
648 #define V4L2_DV_BT_DMT_1680X1050P120_RB { \
649  .type = V4L2_DV_BT_656_1120, \
650  V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
651  245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \
652  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
653  V4L2_DV_FL_REDUCED_BLANKING) \
654 }
655 
656 #define V4L2_DV_BT_DMT_1792X1344P60 { \
657  .type = V4L2_DV_BT_656_1120, \
658  V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
659  204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \
660  V4L2_DV_BT_STD_DMT, 0) \
661 }
662 
663 #define V4L2_DV_BT_DMT_1792X1344P75 { \
664  .type = V4L2_DV_BT_656_1120, \
665  V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
666  261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \
667  V4L2_DV_BT_STD_DMT, 0) \
668 }
669 
670 #define V4L2_DV_BT_DMT_1792X1344P120_RB { \
671  .type = V4L2_DV_BT_656_1120, \
672  V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \
673  333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \
674  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
675  V4L2_DV_FL_REDUCED_BLANKING) \
676 }
677 
678 #define V4L2_DV_BT_DMT_1856X1392P60 { \
679  .type = V4L2_DV_BT_656_1120, \
680  V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
681  218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \
682  V4L2_DV_BT_STD_DMT, 0) \
683 }
684 
685 #define V4L2_DV_BT_DMT_1856X1392P75 { \
686  .type = V4L2_DV_BT_656_1120, \
687  V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
688  288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \
689  V4L2_DV_BT_STD_DMT, 0) \
690 }
691 
692 #define V4L2_DV_BT_DMT_1856X1392P120_RB { \
693  .type = V4L2_DV_BT_656_1120, \
694  V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \
695  356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \
696  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
697  V4L2_DV_FL_REDUCED_BLANKING) \
698 }
699 
700 #define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60
701 
702 /* WUXGA resolutions */
703 #define V4L2_DV_BT_DMT_1920X1200P60_RB { \
704  .type = V4L2_DV_BT_656_1120, \
705  V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
706  154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \
707  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
708  V4L2_DV_FL_REDUCED_BLANKING) \
709 }
710 
711 #define V4L2_DV_BT_DMT_1920X1200P60 { \
712  .type = V4L2_DV_BT_656_1120, \
713  V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
714  193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \
715  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
716 }
717 
718 #define V4L2_DV_BT_DMT_1920X1200P75 { \
719  .type = V4L2_DV_BT_656_1120, \
720  V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
721  245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \
722  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
723 }
724 
725 #define V4L2_DV_BT_DMT_1920X1200P85 { \
726  .type = V4L2_DV_BT_656_1120, \
727  V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
728  281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \
729  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
730 }
731 
732 #define V4L2_DV_BT_DMT_1920X1200P120_RB { \
733  .type = V4L2_DV_BT_656_1120, \
734  V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
735  317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \
736  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
737  V4L2_DV_FL_REDUCED_BLANKING) \
738 }
739 
740 #define V4L2_DV_BT_DMT_1920X1440P60 { \
741  .type = V4L2_DV_BT_656_1120, \
742  V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
743  234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \
744  V4L2_DV_BT_STD_DMT, 0) \
745 }
746 
747 #define V4L2_DV_BT_DMT_1920X1440P75 { \
748  .type = V4L2_DV_BT_656_1120, \
749  V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
750  297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \
751  V4L2_DV_BT_STD_DMT, 0) \
752 }
753 
754 #define V4L2_DV_BT_DMT_1920X1440P120_RB { \
755  .type = V4L2_DV_BT_656_1120, \
756  V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \
757  380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \
758  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
759  V4L2_DV_FL_REDUCED_BLANKING) \
760 }
761 
762 #define V4L2_DV_BT_DMT_2048X1152P60_RB { \
763  .type = V4L2_DV_BT_656_1120, \
764  V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \
765  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
766  162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \
767  V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
768 }
769 
770 /* WQXGA resolutions */
771 #define V4L2_DV_BT_DMT_2560X1600P60_RB { \
772  .type = V4L2_DV_BT_656_1120, \
773  V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
774  268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \
775  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
776  V4L2_DV_FL_REDUCED_BLANKING) \
777 }
778 
779 #define V4L2_DV_BT_DMT_2560X1600P60 { \
780  .type = V4L2_DV_BT_656_1120, \
781  V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
782  348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \
783  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
784 }
785 
786 #define V4L2_DV_BT_DMT_2560X1600P75 { \
787  .type = V4L2_DV_BT_656_1120, \
788  V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
789  443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \
790  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
791 }
792 
793 #define V4L2_DV_BT_DMT_2560X1600P85 { \
794  .type = V4L2_DV_BT_656_1120, \
795  V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
796  505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \
797  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
798 }
799 
800 #define V4L2_DV_BT_DMT_2560X1600P120_RB { \
801  .type = V4L2_DV_BT_656_1120, \
802  V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
803  552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \
804  V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
805  V4L2_DV_FL_REDUCED_BLANKING) \
806 }
807 
808 #define V4L2_DV_BT_DMT_1366X768P60 { \
809  .type = V4L2_DV_BT_656_1120, \
810  V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
811  V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
812  85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \
813  V4L2_DV_BT_STD_DMT, 0) \
814 }
815 
816 #endif
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