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12 #define RESET_WHILE_LOADING 0
16 #define QUICC_MEMCPY_USES_PLX 1
19 #define STATUS_CABLE_V35 2
20 #define STATUS_CABLE_X21 3
21 #define STATUS_CABLE_V24 4
22 #define STATUS_CABLE_EIA530 5
23 #define STATUS_CABLE_INVALID 6
24 #define STATUS_CABLE_NONE 7
26 #define STATUS_CABLE_DCE 0x8000
27 #define STATUS_CABLE_DSR 0x0010
28 #define STATUS_CABLE_DCD 0x0008
29 #define STATUS_CABLE_PM_SHIFT 5
31 #define PDM_OFFSET 0x1000
35 #define RX_QUEUE_LENGTH 40
37 #define PACKET_EMPTY 0x00
38 #define PACKET_FULL 0x10
39 #define PACKET_SENT 0x20
40 #define PACKET_UNDERRUN 0x30
41 #define PACKET_PORT_MASK 0x03
44 #define DOORBELL_FROM_CARD_TX_0 0
45 #define DOORBELL_FROM_CARD_TX_1 1
46 #define DOORBELL_FROM_CARD_TX_2 2
47 #define DOORBELL_FROM_CARD_TX_3 3
48 #define DOORBELL_FROM_CARD_RX 4
49 #define DOORBELL_FROM_CARD_CABLE_0 5
50 #define DOORBELL_FROM_CARD_CABLE_1 6
51 #define DOORBELL_FROM_CARD_CABLE_2 7
52 #define DOORBELL_FROM_CARD_CABLE_3 8
54 #define DOORBELL_TO_CARD_OPEN_0 0
55 #define DOORBELL_TO_CARD_OPEN_1 1
56 #define DOORBELL_TO_CARD_OPEN_2 2
57 #define DOORBELL_TO_CARD_OPEN_3 3
58 #define DOORBELL_TO_CARD_CLOSE_0 4
59 #define DOORBELL_TO_CARD_CLOSE_1 5
60 #define DOORBELL_TO_CARD_CLOSE_2 6
61 #define DOORBELL_TO_CARD_CLOSE_3 7
62 #define DOORBELL_TO_CARD_TX_0 8
63 #define DOORBELL_TO_CARD_TX_1 9
64 #define DOORBELL_TO_CARD_TX_2 10
65 #define DOORBELL_TO_CARD_TX_3 11
73 #define ALIGN32(x) (((x) + 3) & 0xFFFFFFFC)
74 #define BUFFER_LENGTH ALIGN32(HDLC_MAX_MRU + 4)
77 #define BUFFERS_ADDR 0x4000
82 #define PLX_OFFSET PLX + 0x80
85 #define PLX_MAILBOX_0 (PLX_OFFSET + 0x40)
86 #define PLX_MAILBOX_1 (PLX_OFFSET + 0x44)
87 #define PLX_MAILBOX_2 (PLX_OFFSET + 0x48)
88 #define PLX_MAILBOX_3 (PLX_OFFSET + 0x4C)
89 #define PLX_MAILBOX_4 (PLX_OFFSET + 0x50)
90 #define PLX_MAILBOX_5 (PLX_OFFSET + 0x54)
91 #define PLX_MAILBOX_6 (PLX_OFFSET + 0x58)
92 #define PLX_MAILBOX_7 (PLX_OFFSET + 0x5C)
93 #define PLX_DOORBELL_TO_CARD (PLX_OFFSET + 0x60)
94 #define PLX_DOORBELL_FROM_CARD (PLX_OFFSET + 0x64)
95 #define PLX_INTERRUPT_CS (PLX_OFFSET + 0x68)
96 #define PLX_CONTROL (PLX_OFFSET + 0x6C)
99 #define PLX_DMA_0_MODE (PLX + 0x100)
100 #define PLX_DMA_0_PCI (PLX + 0x104)
101 #define PLX_DMA_0_LOCAL (PLX + 0x108)
102 #define PLX_DMA_0_LENGTH (PLX + 0x10C)
103 #define PLX_DMA_0_DESC (PLX + 0x110)
104 #define PLX_DMA_1_MODE (PLX + 0x114)
105 #define PLX_DMA_1_PCI (PLX + 0x118)
106 #define PLX_DMA_1_LOCAL (PLX + 0x11C)
107 #define PLX_DMA_1_LENGTH (PLX + 0x120)
108 #define PLX_DMA_1_DESC (PLX + 0x124)
109 #define PLX_DMA_CMD_STS (PLX + 0x128)
110 #define PLX_DMA_ARBITR_0 (PLX + 0x12C)
111 #define PLX_DMA_ARBITR_1 (PLX + 0x130)
114 #define DESC_LENGTH 12
118 #define STATUS_OPEN 0
119 #define STATUS_CABLE (STATUS_OPEN + 4)
120 #define STATUS_RX_OVERRUNS (STATUS_CABLE + 4)
121 #define STATUS_RX_FRAME_ERRORS (STATUS_RX_OVERRUNS + 4)
124 #define STATUS_PARITY (STATUS_RX_FRAME_ERRORS + 4)
125 #define STATUS_ENCODING (STATUS_PARITY + 4)
126 #define STATUS_CLOCKING (STATUS_ENCODING + 4)
127 #define STATUS_TX_DESCS (STATUS_CLOCKING + 4)
129 #ifndef __ASSEMBLER__