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wb35reg_s.h
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1 #ifndef __WINBOND_WB35REG_S_H
2 #define __WINBOND_WB35REG_S_H
3 
4 #include <linux/spinlock.h>
5 #include <linux/types.h>
6 #include <linux/atomic.h>
7 
8 struct hw_data;
9 
10 /* =========================================================================
11  *
12  * HAL setting function
13  *
14  * ========================================
15  * |Uxx| |Dxx| |Mxx| |BB| |RF|
16  * ========================================
17  * | |
18  * Wb35Reg_Read Wb35Reg_Write
19  *
20  * ----------------------------------------
21  * WbUsb_CallUSBDASync supplied By WbUsb module
22  * ==========================================================================
23  */
24 #define GetBit(dwData, i) (dwData & (0x00000001 << i))
25 #define SetBit(dwData, i) (dwData | (0x00000001 << i))
26 #define ClearBit(dwData, i) (dwData & ~(0x00000001 << i))
27 
28 #define IGNORE_INCREMENT 0
29 #define AUTO_INCREMENT 0
30 #define NO_INCREMENT 1
31 #define REG_DIRECTION(_x, _y) ((_y)->DIRECT == 0 ? usb_rcvctrlpipe(_x, 0) : usb_sndctrlpipe(_x, 0))
32 #define REG_BUF_SIZE(_x) ((_x)->bRequest == 0x04 ? cpu_to_le16((_x)->wLength) : 4)
33 
34 #define BB48_DEFAULT_AL2230_11B 0x0033447c
35 #define BB4C_DEFAULT_AL2230_11B 0x0A00FEFF
36 #define BB48_DEFAULT_AL2230_11G 0x00332C1B
37 #define BB4C_DEFAULT_AL2230_11G 0x0A00FEFF
38 
39 
40 #define BB48_DEFAULT_WB242_11B 0x00292315 /* backoff 2dB */
41 #define BB4C_DEFAULT_WB242_11B 0x0800FEFF /* backoff 2dB */
42 #define BB48_DEFAULT_WB242_11G 0x00453B24
43 #define BB4C_DEFAULT_WB242_11G 0x0E00FEFF
44 
45 /*
46  * ====================================
47  * Default setting for Mxx
48  * ====================================
49  */
50 #define DEFAULT_CWMIN 31 /* (M2C) CWmin. Its value is in the range 0-31. */
51 #define DEFAULT_CWMAX 1023 /* (M2C) CWmax. Its value is in the range 0-1023. */
52 #define DEFAULT_AID 1 /* (M34) AID. Its value is in the range 1-2007. */
53 
54 #define DEFAULT_RATE_RETRY_LIMIT 2 /* (M38) as named */
55 
56 #define DEFAULT_LONG_RETRY_LIMIT 7 /* (M38) LongRetryLimit. Its value is in the range 0-15. */
57 #define DEFAULT_SHORT_RETRY_LIMIT 7 /* (M38) ShortRetryLimit. Its value is in the range 0-15. */
58 #define DEFAULT_PIFST 25 /* (M3C) PIFS Time. Its value is in the range 0-65535. */
59 #define DEFAULT_EIFST 354 /* (M3C) EIFS Time. Its value is in the range 0-1048575. */
60 #define DEFAULT_DIFST 45 /* (M3C) DIFS Time. Its value is in the range 0-65535. */
61 #define DEFAULT_SIFST 5 /* (M3C) SIFS Time. Its value is in the range 0-65535. */
62 #define DEFAULT_OSIFST 10 /* (M3C) Original SIFS Time. Its value is in the range 0-15. */
63 #define DEFAULT_ATIMWD 0 /* (M40) ATIM Window. Its value is in the range 0-65535. */
64 #define DEFAULT_SLOT_TIME 20 /* (M40) ($) SlotTime. Its value is in the range 0-255. */
65 #define DEFAULT_MAX_TX_MSDU_LIFE_TIME 512 /* (M44) MaxTxMSDULifeTime. Its value is in the range 0-4294967295. */
66 #define DEFAULT_BEACON_INTERVAL 500 /* (M48) Beacon Interval. Its value is in the range 0-65535. */
67 #define DEFAULT_PROBE_DELAY_TIME 200 /* (M48) Probe Delay Time. Its value is in the range 0-65535. */
68 #define DEFAULT_PROTOCOL_VERSION 0 /* (M4C) */
69 #define DEFAULT_MAC_POWER_STATE 2 /* (M4C) 2: MAC at power active */
70 #define DEFAULT_DTIM_ALERT_TIME 0
71 
72 
73 struct wb35_reg_queue {
74  struct urb *urb;
75  void *pUsbReq;
76  void *Next;
77  union {
78  u32 VALUE;
79  u32 *pBuffer;
80  };
81  u8 RESERVED[4]; /* space reserved for communication */
82  u16 INDEX; /* For storing the register index */
83  u8 RESERVED_VALID; /* Indicate whether the RESERVED space is valid at this command. */
84  u8 DIRECT; /* 0:In 1:Out */
85 };
86 
87 /*
88  * ====================================
89  * Internal variable for module
90  * ====================================
91  */
92 #define MAX_SQ3_FILTER_SIZE 5
93 struct wb35_reg {
94  /*
95  * ============================
96  * Register Bank backup
97  * ============================
98  */
99  u32 U1B0; /* bit16 record the h/w radio on/off status */
100  u32 U1BC_LEDConfigure;
101  u32 D00_DmaControl;
102  u32 M00_MacControl;
103  union {
104  struct {
105  u32 M04_MulticastAddress1;
106  u32 M08_MulticastAddress2;
107  };
108  u8 Multicast[8]; /* contents of card multicast registers */
109  };
110 
111  u32 M24_MacControl;
112  u32 M28_MacControl;
113  u32 M2C_MacControl;
114  u32 M38_MacControl;
115  u32 M3C_MacControl;
116  u32 M40_MacControl;
117  u32 M44_MacControl;
118  u32 M48_MacControl;
119  u32 M4C_MacStatus;
120  u32 M60_MacControl;
121  u32 M68_MacControl;
122  u32 M70_MacControl;
123  u32 M74_MacControl;
124  u32 M78_ERPInformation;
125  u32 M7C_MacControl;
126  u32 M80_MacControl;
127  u32 M84_MacControl;
128  u32 M88_MacControl;
129  u32 M98_MacControl;
130 
131  /* Baseband register */
132  u32 BB0C; /* Used for LNA calculation */
133  u32 BB2C;
134  u32 BB30; /* 11b acquisition control register */
135  u32 BB3C;
136  u32 BB48;
137  u32 BB4C;
138  u32 BB50; /* mode control register */
139  u32 BB54;
140  u32 BB58; /* IQ_ALPHA */
141  u32 BB5C; /* For test */
142  u32 BB60; /* for WTO read value */
143 
144  /* VM */
145  spinlock_t EP0VM_spin_lock; /* 4B */
146  u32 EP0VM_status; /* $$ */
147  struct wb35_reg_queue *reg_first;
148  struct wb35_reg_queue *reg_last;
149  atomic_t RegFireCount;
150 
151  /* Hardware status */
152  u8 EP0vm_state;
153  u8 mac_power_save;
154  u8 EEPROMPhyType; /*
155  * 0 ~ 15 for Maxim (0 ĄV MAX2825, 1 ĄV MAX2827, 2 ĄV MAX2828, 3 ĄV MAX2829),
156  * 16 ~ 31 for Airoha (16 ĄV AL2230, 11 - AL7230)
157  * 32 ~ Reserved
158  * 33 ~ 47 For WB242 ( 33 - WB242, 34 - WB242 with new Txvga 0.5 db step)
159  * 48 ~ 255 ARE RESERVED.
160  */
161  u8 EEPROMRegion; /* Region setting in EEPROM */
162 
163  u32 SyncIoPause; /* If user use the Sync Io to access Hw, then pause the async access */
164 
165  u8 LNAValue[4]; /* Table for speed up running */
166  u32 SQ3_filter[MAX_SQ3_FILTER_SIZE];
167  u32 SQ3_index;
168 };
169 
170 /* =====================================================================
171  * Function declaration
172  * =====================================================================
173  */
174 void hal_remove_mapping_key(struct hw_data *hw_data, u8 *mac_addr);
175 void hal_remove_default_key(struct hw_data *hw_data, u32 index);
176 unsigned char hal_set_mapping_key(struct hw_data *adapter, u8 *mac_addr,
177  u8 null_key, u8 wep_on, u8 *tx_tsc,
178  u8 *rx_tsc, u8 key_type, u8 key_len,
179  u8 *key_data);
180 unsigned char hal_set_default_key(struct hw_data *adapter, u8 index,
181  u8 null_key, u8 wep_on, u8 *tx_tsc,
182  u8 *rx_tsc, u8 key_type, u8 key_len,
183  u8 *key_data);
184 void hal_clear_all_default_key(struct hw_data *hw_data);
185 void hal_clear_all_group_key(struct hw_data *hw_data);
186 void hal_clear_all_mapping_key(struct hw_data *hw_data);
187 void hal_clear_all_key(struct hw_data *hw_data);
188 void hal_set_power_save_mode(struct hw_data *hw_data, unsigned char power_save,
189  unsigned char wakeup, unsigned char dtim);
190 void hal_get_power_save_mode(struct hw_data *hw_data, u8 *in_pwr_save);
191 void hal_set_slot_time(struct hw_data *hw_data, u8 type);
192 
193 #define hal_set_atim_window(_A, _ATM)
194 
195 void hal_start_bss(struct hw_data *hw_data, u8 mac_op_mode);
196 
197 /* 0:BSS STA 1:IBSS STA */
198 void hal_join_request(struct hw_data *hw_data, u8 bss_type);
199 
200 void hal_stop_sync_bss(struct hw_data *hw_data);
201 void hal_resume_sync_bss(struct hw_data *hw_data);
202 void hal_set_aid(struct hw_data *hw_data, u16 aid);
203 void hal_set_bssid(struct hw_data *hw_data, u8 *bssid);
204 void hal_get_bssid(struct hw_data *hw_data, u8 *bssid);
205 void hal_set_listen_interval(struct hw_data *hw_data, u16 listen_interval);
206 void hal_set_cap_info(struct hw_data *hw_data, u16 capability_info);
207 void hal_set_ssid(struct hw_data *hw_data, u8 *ssid, u8 ssid_len);
208 void hal_start_tx0(struct hw_data *hw_data);
209 
210 #define hal_get_cwmin(_A) ((_A)->cwmin)
211 
212 void hal_set_cwmax(struct hw_data *hw_data, u16 cwin_max);
213 
214 #define hal_get_cwmax(_A) ((_A)->cwmax)
215 
216 void hal_set_rsn_wpa(struct hw_data *hw_data, u32 *rsn_ie_bitmap,
217  u32 *rsn_oui_type , unsigned char desired_auth_mode);
218 void hal_set_connect_info(struct hw_data *hw_data, unsigned char bo_connect);
219 u8 hal_get_est_sq3(struct hw_data *hw_data, u8 count);
220 void hal_descriptor_indicate(struct hw_data *hw_data,
221  struct wb35_descriptor *des);
222 u8 hal_get_antenna_number(struct hw_data *hw_data);
223 u32 hal_get_bss_pk_cnt(struct hw_data *hw_data);
224 
225 #define hal_get_region_from_EEPROM(_A) ((_A)->reg.EEPROMRegion)
226 #define hal_get_tx_buffer(_A, _B) Wb35Tx_get_tx_buffer(_A, _B)
227 #define hal_software_set(_A) (_A->SoftwareSet)
228 #define hal_driver_init_OK(_A) (_A->IsInitOK)
229 #define hal_rssi_boundary_high(_A) (_A->RSSI_high)
230 #define hal_rssi_boundary_low(_A) (_A->RSSI_low)
231 #define hal_scan_interval(_A) (_A->Scan_Interval)
232 
233 #define PHY_DEBUG(msg, args...)
234 
235 /* return 100ms count */
236 #define hal_get_time_count(_P) (_P->time_count / 10)
237 
238 #define hal_ibss_disconnect(_A) (hal_stop_sync_bss(_A))
239 
240 #endif
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