21 #include <linux/errno.h>
22 #include <linux/module.h>
28 #include <asm/paravirt.h>
31 #include <asm/setup.h>
32 #include <asm/pgtable.h>
34 #include <asm/pgalloc.h>
36 #include <asm/delay.h>
37 #include <asm/fixmap.h>
39 #include <asm/tlbflush.h>
40 #include <asm/timer.h>
41 #include <asm/special_insns.h>
66 #define DEF_NATIVE(ops, name, code) \
67 extern const char start_##ops##_##name[], end_##ops##_##name[]; \
68 asm("start_" #ops "_" #name ": " code "; end_" #ops "_" #name ":")
71 static const unsigned char ud2a[] = { 0x0f, 0x0b };
90 unsigned long addr,
u16 site_clobbers,
94 unsigned long delta = (
unsigned long)target - (addr+5);
96 if (tgt_clobbers & ~site_clobbers)
109 unsigned long addr,
unsigned len)
112 unsigned long delta = (
unsigned long)target - (addr+5);
125 static void *get_call_destination(
u8 type)
134 #ifdef CONFIG_PARAVIRT_SPINLOCKS
138 return *((
void **)&tmpl + type);
142 unsigned long addr,
unsigned len)
144 void *opfunc = get_call_destination(type);
170 addr, clobbers, len);
178 unsigned insn_len = end -
start;
180 if (insn_len > len || start ==
NULL)
183 memcpy(insnbuf, start, insn_len);
188 static void native_flush_tlb(
void)
190 __native_flush_tlb();
197 static void native_flush_tlb_global(
void)
199 __native_flush_tlb_global();
202 static void native_flush_tlb_single(
unsigned long addr)
204 __native_flush_tlb_single(addr);
210 static u64 native_steal_clock(
int cpu)
221 static struct resource reserve_ioports = {
224 .name =
"paravirt-ioport",
308 .
name =
"bare hardware",
309 .paravirt_enabled = 0,
311 .shared_kernel_pmd = 1,
324 .steal_clock = native_steal_clock,
328 .
save_fl = __PV_IS_CALLEE_SAVE(native_save_fl),
329 .restore_fl = __PV_IS_CALLEE_SAVE(native_restore_fl),
330 .irq_disable = __PV_IS_CALLEE_SAVE(native_irq_disable),
331 .irq_enable = __PV_IS_CALLEE_SAVE(native_irq_enable),
332 .safe_halt = native_safe_halt,
340 .
cpuid = native_cpuid,
341 .get_debugreg = native_get_debugreg,
342 .set_debugreg = native_set_debugreg,
344 .read_cr0 = native_read_cr0,
345 .write_cr0 = native_write_cr0,
346 .read_cr4 = native_read_cr4,
347 .read_cr4_safe = native_read_cr4_safe,
348 .write_cr4 = native_write_cr4,
350 .read_cr8 = native_read_cr8,
351 .write_cr8 = native_write_cr8,
353 .wbinvd = native_wbinvd,
354 .read_msr = native_read_msr_safe,
355 .write_msr = native_write_msr_safe,
357 .read_pmc = native_read_pmc,
358 .read_tscp = native_read_tscp,
359 .load_tr_desc = native_load_tr_desc,
360 .set_ldt = native_set_ldt,
361 .load_gdt = native_load_gdt,
362 .load_idt = native_load_idt,
363 .store_gdt = native_store_gdt,
364 .store_idt = native_store_idt,
365 .store_tr = native_store_tr,
366 .load_tls = native_load_tls,
368 .load_gs_index = native_load_gs_index,
370 .write_ldt_entry = native_write_ldt_entry,
371 .write_gdt_entry = native_write_gdt_entry,
372 .write_idt_entry = native_write_idt_entry,
377 .load_sp0 = native_load_sp0,
379 #if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION)
383 #ifdef CONFIG_IA32_EMULATION
389 .swapgs = native_swapgs,
391 .set_iopl_mask = native_set_iopl_mask,
399 #ifdef CONFIG_X86_LOCAL_APIC
404 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
406 #define PTE_IDENT __PV_IS_CALLEE_SAVE(_paravirt_ident_32)
409 #define PTE_IDENT __PV_IS_CALLEE_SAVE(_paravirt_ident_64)
415 .write_cr2 = native_write_cr2,
416 .read_cr3 = native_read_cr3,
417 .write_cr3 = native_write_cr3,
419 .flush_tlb_user = native_flush_tlb,
420 .flush_tlb_kernel = native_flush_tlb_global,
421 .flush_tlb_single = native_flush_tlb_single,
424 .pgd_alloc = __paravirt_pgd_alloc,
434 .set_pte = native_set_pte,
435 .set_pte_at = native_set_pte_at,
436 .set_pmd = native_set_pmd,
437 .set_pmd_at = native_set_pmd_at,
443 .ptep_modify_prot_start = __ptep_modify_prot_start,
444 .ptep_modify_prot_commit = __ptep_modify_prot_commit,
446 #if PAGETABLE_LEVELS >= 3
447 #ifdef CONFIG_X86_PAE
448 .set_pte_atomic = native_set_pte_atomic,
449 .pte_clear = native_pte_clear,
450 .pmd_clear = native_pmd_clear,
452 .set_pud = native_set_pud,
457 #if PAGETABLE_LEVELS == 4
461 .set_pgd = native_set_pgd,