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xbow.h
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1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License. See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1992-1997,2000-2006 Silicon Graphics, Inc. All Rights
7  * Reserved.
8  */
9 #ifndef _ASM_IA64_SN_XTALK_XBOW_H
10 #define _ASM_IA64_SN_XTALK_XBOW_H
11 
12 #define XBOW_PORT_8 0x8
13 #define XBOW_PORT_C 0xc
14 #define XBOW_PORT_F 0xf
15 
16 #define MAX_XBOW_PORTS 8 /* number of ports on xbow chip */
17 #define BASE_XBOW_PORT XBOW_PORT_8 /* Lowest external port */
18 
19 #define XBOW_CREDIT 4
20 
21 #define MAX_XBOW_NAME 16
22 
23 /* Register set for each xbow link */
24 typedef volatile struct xb_linkregs_s {
25 /*
26  * we access these through synergy unswizzled space, so the address
27  * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
28  * That's why we put the register first and filler second.
29  */
30  u32 link_ibf;
31  u32 filler0; /* filler for proper alignment */
32  u32 link_control;
33  u32 filler1;
34  u32 link_status;
35  u32 filler2;
36  u32 link_arb_upper;
37  u32 filler3;
38  u32 link_arb_lower;
39  u32 filler4;
40  u32 link_status_clr;
41  u32 filler5;
42  u32 link_reset;
43  u32 filler6;
44  u32 link_aux_status;
45  u32 filler7;
46 } xb_linkregs_t;
47 
48 typedef volatile struct xbow_s {
49  /* standard widget configuration 0x000000-0x000057 */
50  struct widget_cfg xb_widget; /* 0x000000 */
51 
52  /* helper fieldnames for accessing bridge widget */
53 
54 #define xb_wid_id xb_widget.w_id
55 #define xb_wid_stat xb_widget.w_status
56 #define xb_wid_err_upper xb_widget.w_err_upper_addr
57 #define xb_wid_err_lower xb_widget.w_err_lower_addr
58 #define xb_wid_control xb_widget.w_control
59 #define xb_wid_req_timeout xb_widget.w_req_timeout
60 #define xb_wid_int_upper xb_widget.w_intdest_upper_addr
61 #define xb_wid_int_lower xb_widget.w_intdest_lower_addr
62 #define xb_wid_err_cmdword xb_widget.w_err_cmd_word
63 #define xb_wid_llp xb_widget.w_llp_cfg
64 #define xb_wid_stat_clr xb_widget.w_tflush
65 
66 /*
67  * we access these through synergy unswizzled space, so the address
68  * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
69  * That's why we put the register first and filler second.
70  */
71  /* xbow-specific widget configuration 0x000058-0x0000FF */
72  u32 xb_wid_arb_reload; /* 0x00005C */
73  u32 _pad_000058;
74  u32 xb_perf_ctr_a; /* 0x000064 */
75  u32 _pad_000060;
76  u32 xb_perf_ctr_b; /* 0x00006c */
77  u32 _pad_000068;
78  u32 xb_nic; /* 0x000074 */
79  u32 _pad_000070;
80 
81  /* Xbridge only */
82  u32 xb_w0_rst_fnc; /* 0x00007C */
83  u32 _pad_000078;
84  u32 xb_l8_rst_fnc; /* 0x000084 */
85  u32 _pad_000080;
86  u32 xb_l9_rst_fnc; /* 0x00008c */
87  u32 _pad_000088;
88  u32 xb_la_rst_fnc; /* 0x000094 */
89  u32 _pad_000090;
90  u32 xb_lb_rst_fnc; /* 0x00009c */
91  u32 _pad_000098;
92  u32 xb_lc_rst_fnc; /* 0x0000a4 */
93  u32 _pad_0000a0;
94  u32 xb_ld_rst_fnc; /* 0x0000ac */
95  u32 _pad_0000a8;
96  u32 xb_le_rst_fnc; /* 0x0000b4 */
97  u32 _pad_0000b0;
98  u32 xb_lf_rst_fnc; /* 0x0000bc */
99  u32 _pad_0000b8;
100  u32 xb_lock; /* 0x0000c4 */
101  u32 _pad_0000c0;
102  u32 xb_lock_clr; /* 0x0000cc */
103  u32 _pad_0000c8;
104  /* end of Xbridge only */
105  u32 _pad_0000d0[12];
106 
107  /* Link Specific Registers, port 8..15 0x000100-0x000300 */
108  xb_linkregs_t xb_link_raw[MAX_XBOW_PORTS];
109 } xbow_t;
110 
111 #define xb_link(p) xb_link_raw[(p) & (MAX_XBOW_PORTS - 1)]
112 
113 #define XB_FLAGS_EXISTS 0x1 /* device exists */
114 #define XB_FLAGS_MASTER 0x2
115 #define XB_FLAGS_SLAVE 0x0
116 #define XB_FLAGS_GBR 0x4
117 #define XB_FLAGS_16BIT 0x8
118 #define XB_FLAGS_8BIT 0x0
119 
120 /* is widget port number valid? (based on version 7.0 of xbow spec) */
121 #define XBOW_WIDGET_IS_VALID(wid) ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_F)
122 
123 /* whether to use upper or lower arbitration register, given source widget id */
124 #define XBOW_ARB_IS_UPPER(wid) ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_B)
125 #define XBOW_ARB_IS_LOWER(wid) ((wid) >= XBOW_PORT_C && (wid) <= XBOW_PORT_F)
126 
127 /* offset of arbitration register, given source widget id */
128 #define XBOW_ARB_OFF(wid) (XBOW_ARB_IS_UPPER(wid) ? 0x1c : 0x24)
129 
130 #define XBOW_WID_ID WIDGET_ID
131 #define XBOW_WID_STAT WIDGET_STATUS
132 #define XBOW_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR
133 #define XBOW_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR
134 #define XBOW_WID_CONTROL WIDGET_CONTROL
135 #define XBOW_WID_REQ_TO WIDGET_REQ_TIMEOUT
136 #define XBOW_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR
137 #define XBOW_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR
138 #define XBOW_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD
139 #define XBOW_WID_LLP WIDGET_LLP_CFG
140 #define XBOW_WID_STAT_CLR WIDGET_TFLUSH
141 #define XBOW_WID_ARB_RELOAD 0x5c
142 #define XBOW_WID_PERF_CTR_A 0x64
143 #define XBOW_WID_PERF_CTR_B 0x6c
144 #define XBOW_WID_NIC 0x74
145 
146 /* Xbridge only */
147 #define XBOW_W0_RST_FNC 0x00007C
148 #define XBOW_L8_RST_FNC 0x000084
149 #define XBOW_L9_RST_FNC 0x00008c
150 #define XBOW_LA_RST_FNC 0x000094
151 #define XBOW_LB_RST_FNC 0x00009c
152 #define XBOW_LC_RST_FNC 0x0000a4
153 #define XBOW_LD_RST_FNC 0x0000ac
154 #define XBOW_LE_RST_FNC 0x0000b4
155 #define XBOW_LF_RST_FNC 0x0000bc
156 #define XBOW_RESET_FENCE(x) ((x) > 7 && (x) < 16) ? \
157  (XBOW_W0_RST_FNC + ((x) - 7) * 8) : \
158  ((x) == 0) ? XBOW_W0_RST_FNC : 0
159 #define XBOW_LOCK 0x0000c4
160 #define XBOW_LOCK_CLR 0x0000cc
161 /* End of Xbridge only */
162 
163 /* used only in ide, but defined here within the reserved portion */
164 /* of the widget0 address space (before 0xf4) */
165 #define XBOW_WID_UNDEF 0xe4
166 
167 /* xbow link register set base, legal value for x is 0x8..0xf */
168 #define XB_LINK_BASE 0x100
169 #define XB_LINK_OFFSET 0x40
170 #define XB_LINK_REG_BASE(x) (XB_LINK_BASE + ((x) & (MAX_XBOW_PORTS - 1)) * XB_LINK_OFFSET)
171 
172 #define XB_LINK_IBUF_FLUSH(x) (XB_LINK_REG_BASE(x) + 0x4)
173 #define XB_LINK_CTRL(x) (XB_LINK_REG_BASE(x) + 0xc)
174 #define XB_LINK_STATUS(x) (XB_LINK_REG_BASE(x) + 0x14)
175 #define XB_LINK_ARB_UPPER(x) (XB_LINK_REG_BASE(x) + 0x1c)
176 #define XB_LINK_ARB_LOWER(x) (XB_LINK_REG_BASE(x) + 0x24)
177 #define XB_LINK_STATUS_CLR(x) (XB_LINK_REG_BASE(x) + 0x2c)
178 #define XB_LINK_RESET(x) (XB_LINK_REG_BASE(x) + 0x34)
179 #define XB_LINK_AUX_STATUS(x) (XB_LINK_REG_BASE(x) + 0x3c)
180 
181 /* link_control(x) */
182 #define XB_CTRL_LINKALIVE_IE 0x80000000 /* link comes alive */
183 /* reserved: 0x40000000 */
184 #define XB_CTRL_PERF_CTR_MODE_MSK 0x30000000 /* perf counter mode */
185 #define XB_CTRL_IBUF_LEVEL_MSK 0x0e000000 /* input packet buffer
186  level */
187 #define XB_CTRL_8BIT_MODE 0x01000000 /* force link into 8
188  bit mode */
189 #define XB_CTRL_BAD_LLP_PKT 0x00800000 /* force bad LLP
190  packet */
191 #define XB_CTRL_WIDGET_CR_MSK 0x007c0000 /* LLP widget credit
192  mask */
193 #define XB_CTRL_WIDGET_CR_SHFT 18 /* LLP widget credit
194  shift */
195 #define XB_CTRL_ILLEGAL_DST_IE 0x00020000 /* illegal destination
196  */
197 #define XB_CTRL_OALLOC_IBUF_IE 0x00010000 /* overallocated input
198  buffer */
199 /* reserved: 0x0000fe00 */
200 #define XB_CTRL_BNDWDTH_ALLOC_IE 0x00000100 /* bandwidth alloc */
201 #define XB_CTRL_RCV_CNT_OFLOW_IE 0x00000080 /* rcv retry overflow */
202 #define XB_CTRL_XMT_CNT_OFLOW_IE 0x00000040 /* xmt retry overflow */
203 #define XB_CTRL_XMT_MAX_RTRY_IE 0x00000020 /* max transmit retry */
204 #define XB_CTRL_RCV_IE 0x00000010 /* receive */
205 #define XB_CTRL_XMT_RTRY_IE 0x00000008 /* transmit retry */
206 /* reserved: 0x00000004 */
207 #define XB_CTRL_MAXREQ_TOUT_IE 0x00000002 /* maximum request
208  timeout */
209 #define XB_CTRL_SRC_TOUT_IE 0x00000001 /* source timeout */
210 
211 /* link_status(x) */
212 #define XB_STAT_LINKALIVE XB_CTRL_LINKALIVE_IE
213 /* reserved: 0x7ff80000 */
214 #define XB_STAT_MULTI_ERR 0x00040000 /* multi error */
215 #define XB_STAT_ILLEGAL_DST_ERR XB_CTRL_ILLEGAL_DST_IE
216 #define XB_STAT_OALLOC_IBUF_ERR XB_CTRL_OALLOC_IBUF_IE
217 #define XB_STAT_BNDWDTH_ALLOC_ID_MSK 0x0000ff00 /* port bitmask */
218 #define XB_STAT_RCV_CNT_OFLOW_ERR XB_CTRL_RCV_CNT_OFLOW_IE
219 #define XB_STAT_XMT_CNT_OFLOW_ERR XB_CTRL_XMT_CNT_OFLOW_IE
220 #define XB_STAT_XMT_MAX_RTRY_ERR XB_CTRL_XMT_MAX_RTRY_IE
221 #define XB_STAT_RCV_ERR XB_CTRL_RCV_IE
222 #define XB_STAT_XMT_RTRY_ERR XB_CTRL_XMT_RTRY_IE
223 /* reserved: 0x00000004 */
224 #define XB_STAT_MAXREQ_TOUT_ERR XB_CTRL_MAXREQ_TOUT_IE
225 #define XB_STAT_SRC_TOUT_ERR XB_CTRL_SRC_TOUT_IE
226 
227 /* link_aux_status(x) */
228 #define XB_AUX_STAT_RCV_CNT 0xff000000
229 #define XB_AUX_STAT_XMT_CNT 0x00ff0000
230 #define XB_AUX_STAT_TOUT_DST 0x0000ff00
231 #define XB_AUX_LINKFAIL_RST_BAD 0x00000040
232 #define XB_AUX_STAT_PRESENT 0x00000020
233 #define XB_AUX_STAT_PORT_WIDTH 0x00000010
234 /* reserved: 0x0000000f */
235 
236 /*
237  * link_arb_upper/link_arb_lower(x), (reg) should be the link_arb_upper
238  * register if (x) is 0x8..0xb, link_arb_lower if (x) is 0xc..0xf
239  */
240 #define XB_ARB_GBR_MSK 0x1f
241 #define XB_ARB_RR_MSK 0x7
242 #define XB_ARB_GBR_SHFT(x) (((x) & 0x3) * 8)
243 #define XB_ARB_RR_SHFT(x) (((x) & 0x3) * 8 + 5)
244 #define XB_ARB_GBR_CNT(reg,x) ((reg) >> XB_ARB_GBR_SHFT(x) & XB_ARB_GBR_MSK)
245 #define XB_ARB_RR_CNT(reg,x) ((reg) >> XB_ARB_RR_SHFT(x) & XB_ARB_RR_MSK)
246 
247 /* XBOW_WID_STAT */
248 #define XB_WID_STAT_LINK_INTR_SHFT (24)
249 #define XB_WID_STAT_LINK_INTR_MASK (0xFF << XB_WID_STAT_LINK_INTR_SHFT)
250 #define XB_WID_STAT_LINK_INTR(x) \
251  (0x1 << (((x)&7) + XB_WID_STAT_LINK_INTR_SHFT))
252 #define XB_WID_STAT_WIDGET0_INTR 0x00800000
253 #define XB_WID_STAT_SRCID_MASK 0x000003c0 /* Xbridge only */
254 #define XB_WID_STAT_REG_ACC_ERR 0x00000020
255 #define XB_WID_STAT_RECV_TOUT 0x00000010 /* Xbridge only */
256 #define XB_WID_STAT_ARB_TOUT 0x00000008 /* Xbridge only */
257 #define XB_WID_STAT_XTALK_ERR 0x00000004
258 #define XB_WID_STAT_DST_TOUT 0x00000002 /* Xbridge only */
259 #define XB_WID_STAT_MULTI_ERR 0x00000001
260 
261 #define XB_WID_STAT_SRCID_SHFT 6
262 
263 /* XBOW_WID_CONTROL */
264 #define XB_WID_CTRL_REG_ACC_IE XB_WID_STAT_REG_ACC_ERR
265 #define XB_WID_CTRL_RECV_TOUT XB_WID_STAT_RECV_TOUT
266 #define XB_WID_CTRL_ARB_TOUT XB_WID_STAT_ARB_TOUT
267 #define XB_WID_CTRL_XTALK_IE XB_WID_STAT_XTALK_ERR
268 
269 /* XBOW_WID_INT_UPPER */
270 /* defined in xwidget.h for WIDGET_INTDEST_UPPER_ADDR */
271 
272 /* XBOW WIDGET part number, in the ID register */
273 #define XBOW_WIDGET_PART_NUM 0x0 /* crossbow */
274 #define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbridge */
275 #define XBOW_WIDGET_MFGR_NUM 0x0
276 #define XXBOW_WIDGET_MFGR_NUM 0x0
277 #define PXBOW_WIDGET_PART_NUM 0xd100 /* PIC */
278 
279 #define XBOW_REV_1_0 0x1 /* xbow rev 1.0 is "1" */
280 #define XBOW_REV_1_1 0x2 /* xbow rev 1.1 is "2" */
281 #define XBOW_REV_1_2 0x3 /* xbow rev 1.2 is "3" */
282 #define XBOW_REV_1_3 0x4 /* xbow rev 1.3 is "4" */
283 #define XBOW_REV_2_0 0x5 /* xbow rev 2.0 is "5" */
284 
285 #define XXBOW_PART_REV_1_0 (XXBOW_WIDGET_PART_NUM << 4 | 0x1 )
286 #define XXBOW_PART_REV_2_0 (XXBOW_WIDGET_PART_NUM << 4 | 0x2 )
287 
288 /* XBOW_WID_ARB_RELOAD */
289 #define XBOW_WID_ARB_RELOAD_INT 0x3f /* GBR reload interval */
290 
291 #define IS_XBRIDGE_XBOW(wid) \
292  (XWIDGET_PART_NUM(wid) == XXBOW_WIDGET_PART_NUM && \
293  XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM)
294 
295 #define IS_PIC_XBOW(wid) \
296  (XWIDGET_PART_NUM(wid) == PXBOW_WIDGET_PART_NUM && \
297  XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM)
298 
299 #define XBOW_WAR_ENABLED(pv, widid) ((1 << XWIDGET_REV_NUM(widid)) & pv)
300 
301 #endif /* _ASM_IA64_SN_XTALK_XBOW_H */
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