LLVM API Documentation

LiveIntervalUnion.cpp
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00001 //===-- LiveIntervalUnion.cpp - Live interval union data structure --------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // LiveIntervalUnion represents a coalesced set of live intervals. This may be
00011 // used during coalescing to represent a congruence class, or during register
00012 // allocation to model liveness of a physical register.
00013 //
00014 //===----------------------------------------------------------------------===//
00015 
00016 #include "llvm/CodeGen/LiveIntervalUnion.h"
00017 #include "llvm/ADT/SparseBitVector.h"
00018 #include "llvm/Support/Debug.h"
00019 #include "llvm/Support/raw_ostream.h"
00020 #include "llvm/Target/TargetRegisterInfo.h"
00021 #include <algorithm>
00022 
00023 using namespace llvm;
00024 
00025 #define DEBUG_TYPE "regalloc"
00026 
00027 
00028 // Merge a LiveInterval's segments. Guarantee no overlaps.
00029 void LiveIntervalUnion::unify(LiveInterval &VirtReg) {
00030   if (VirtReg.empty())
00031     return;
00032   ++Tag;
00033 
00034   // Insert each of the virtual register's live segments into the map.
00035   LiveInterval::iterator RegPos = VirtReg.begin();
00036   LiveInterval::iterator RegEnd = VirtReg.end();
00037   SegmentIter SegPos = Segments.find(RegPos->start);
00038 
00039   while (SegPos.valid()) {
00040     SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
00041     if (++RegPos == RegEnd)
00042       return;
00043     SegPos.advanceTo(RegPos->start);
00044   }
00045 
00046   // We have reached the end of Segments, so it is no longer necessary to search
00047   // for the insertion position.
00048   // It is faster to insert the end first.
00049   --RegEnd;
00050   SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
00051   for (; RegPos != RegEnd; ++RegPos, ++SegPos)
00052     SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
00053 }
00054 
00055 // Remove a live virtual register's segments from this union.
00056 void LiveIntervalUnion::extract(LiveInterval &VirtReg) {
00057   if (VirtReg.empty())
00058     return;
00059   ++Tag;
00060 
00061   // Remove each of the virtual register's live segments from the map.
00062   LiveInterval::iterator RegPos = VirtReg.begin();
00063   LiveInterval::iterator RegEnd = VirtReg.end();
00064   SegmentIter SegPos = Segments.find(RegPos->start);
00065 
00066   for (;;) {
00067     assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval");
00068     SegPos.erase();
00069     if (!SegPos.valid())
00070       return;
00071 
00072     // Skip all segments that may have been coalesced.
00073     RegPos = VirtReg.advanceTo(RegPos, SegPos.start());
00074     if (RegPos == RegEnd)
00075       return;
00076 
00077     SegPos.advanceTo(RegPos->start);
00078   }
00079 }
00080 
00081 void
00082 LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
00083   if (empty()) {
00084     OS << " empty\n";
00085     return;
00086   }
00087   for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
00088     OS << " [" << SI.start() << ' ' << SI.stop() << "):"
00089        << PrintReg(SI.value()->reg, TRI);
00090   }
00091   OS << '\n';
00092 }
00093 
00094 #ifndef NDEBUG
00095 // Verify the live intervals in this union and add them to the visited set.
00096 void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {
00097   for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI)
00098     VisitedVRegs.set(SI.value()->reg);
00099 }
00100 #endif //!NDEBUG
00101 
00102 // Scan the vector of interfering virtual registers in this union. Assume it's
00103 // quite small.
00104 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const {
00105   SmallVectorImpl<LiveInterval*>::const_iterator I =
00106     std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg);
00107   return I != InterferingVRegs.end();
00108 }
00109 
00110 // Collect virtual registers in this union that interfere with this
00111 // query's live virtual register.
00112 //
00113 // The query state is one of:
00114 //
00115 // 1. CheckedFirstInterference == false: Iterators are uninitialized.
00116 // 2. SeenAllInterferences == true: InterferingVRegs complete, iterators unused.
00117 // 3. Iterators left at the last seen intersection.
00118 //
00119 unsigned LiveIntervalUnion::Query::
00120 collectInterferingVRegs(unsigned MaxInterferingRegs) {
00121   // Fast path return if we already have the desired information.
00122   if (SeenAllInterferences || InterferingVRegs.size() >= MaxInterferingRegs)
00123     return InterferingVRegs.size();
00124 
00125   // Set up iterators on the first call.
00126   if (!CheckedFirstInterference) {
00127     CheckedFirstInterference = true;
00128 
00129     // Quickly skip interference check for empty sets.
00130     if (VirtReg->empty() || LiveUnion->empty()) {
00131       SeenAllInterferences = true;
00132       return 0;
00133     }
00134 
00135     // In most cases, the union will start before VirtReg.
00136     VirtRegI = VirtReg->begin();
00137     LiveUnionI.setMap(LiveUnion->getMap());
00138     LiveUnionI.find(VirtRegI->start);
00139   }
00140 
00141   LiveInterval::iterator VirtRegEnd = VirtReg->end();
00142   LiveInterval *RecentReg = nullptr;
00143   while (LiveUnionI.valid()) {
00144     assert(VirtRegI != VirtRegEnd && "Reached end of VirtReg");
00145 
00146     // Check for overlapping interference.
00147     while (VirtRegI->start < LiveUnionI.stop() &&
00148            VirtRegI->end > LiveUnionI.start()) {
00149       // This is an overlap, record the interfering register.
00150       LiveInterval *VReg = LiveUnionI.value();
00151       if (VReg != RecentReg && !isSeenInterference(VReg)) {
00152         RecentReg = VReg;
00153         InterferingVRegs.push_back(VReg);
00154         if (InterferingVRegs.size() >= MaxInterferingRegs)
00155           return InterferingVRegs.size();
00156       }
00157       // This LiveUnion segment is no longer interesting.
00158       if (!(++LiveUnionI).valid()) {
00159         SeenAllInterferences = true;
00160         return InterferingVRegs.size();
00161       }
00162     }
00163 
00164     // The iterators are now not overlapping, LiveUnionI has been advanced
00165     // beyond VirtRegI.
00166     assert(VirtRegI->end <= LiveUnionI.start() && "Expected non-overlap");
00167 
00168     // Advance the iterator that ends first.
00169     VirtRegI = VirtReg->advanceTo(VirtRegI, LiveUnionI.start());
00170     if (VirtRegI == VirtRegEnd)
00171       break;
00172 
00173     // Detect overlap, handle above.
00174     if (VirtRegI->start < LiveUnionI.stop())
00175       continue;
00176 
00177     // Still not overlapping. Catch up LiveUnionI.
00178     LiveUnionI.advanceTo(VirtRegI->start);
00179   }
00180   SeenAllInterferences = true;
00181   return InterferingVRegs.size();
00182 }
00183 
00184 void LiveIntervalUnion::Array::init(LiveIntervalUnion::Allocator &Alloc,
00185                                     unsigned NSize) {
00186   // Reuse existing allocation.
00187   if (NSize == Size)
00188     return;
00189   clear();
00190   Size = NSize;
00191   LIUs = static_cast<LiveIntervalUnion*>(
00192     malloc(sizeof(LiveIntervalUnion)*NSize));
00193   for (unsigned i = 0; i != Size; ++i)
00194     new(LIUs + i) LiveIntervalUnion(Alloc);
00195 }
00196 
00197 void LiveIntervalUnion::Array::clear() {
00198   if (!LIUs)
00199     return;
00200   for (unsigned i = 0; i != Size; ++i)
00201     LIUs[i].~LiveIntervalUnion();
00202   free(LIUs);
00203   Size =  0;
00204   LIUs = nullptr;
00205 }