#include <TargetRegisterInfo.h>
Detailed Description
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDesc objects that represent all of the machine registers that the target has. As such, we simply have to track a pointer to this array so that we can turn register number into a register descriptor.
Definition at line 219 of file TargetRegisterInfo.h.
Member Typedef Documentation
Reimplemented from llvm::MCRegisterInfo.
Definition at line 221 of file TargetRegisterInfo.h.
Constructor & Destructor Documentation
| TargetRegisterInfo::TargetRegisterInfo | ( | const TargetRegisterInfoDesc * | ID, |
| regclass_iterator | RegClassBegin, | ||
| regclass_iterator | RegClassEnd, | ||
| const char *const * | SRINames, | ||
| const unsigned * | SRILaneMasks, | ||
| unsigned | CoveringLanes | ||
| ) | [protected] |
Definition at line 23 of file TargetRegisterInfo.cpp.
| TargetRegisterInfo::~TargetRegisterInfo | ( | ) | [protected, virtual] |
Definition at line 34 of file TargetRegisterInfo.cpp.
Member Function Documentation
| virtual bool llvm::TargetRegisterInfo::avoidWriteAfterWrite | ( | const TargetRegisterClass * | RC | ) | const [inline, virtual] |
avoidWriteAfterWrite - Return true if the register allocator should avoid writing a register from RC in two consecutive instructions. This can avoid pipeline stalls on certain architectures. It does cause increased register pressure, though.
Definition at line 660 of file TargetRegisterInfo.h.
| unsigned llvm::TargetRegisterInfo::composeSubRegIndices | ( | unsigned | a, |
| unsigned | b | ||
| ) | const [inline] |
composeSubRegIndices - Return the subregister index you get from composing two subregister indices.
The special null sub-register index composes as the identity.
If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) returns c. Note that composeSubRegIndices does not tell you about illegal compositions. If R does not have a subreg a, or R:a does not have a subreg b, composeSubRegIndices doesn't tell you.
The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has ssub_0:S0 - ssub_3:S3 subregs. If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
Definition at line 503 of file TargetRegisterInfo.h.
References composeSubRegIndicesImpl().
Referenced by getCommonSuperRegClass(), llvm::CoalescerPair::isCoalescable(), and llvm::MachineOperand::substVirtReg().
| virtual unsigned llvm::TargetRegisterInfo::composeSubRegIndicesImpl | ( | unsigned | , |
| unsigned | |||
| ) | const [inline, protected, virtual] |
Overridden by TableGen in targets that have sub-registers.
Definition at line 511 of file TargetRegisterInfo.h.
References llvm_unreachable.
Referenced by composeSubRegIndices().
| virtual void llvm::TargetRegisterInfo::eliminateFrameIndex | ( | MachineBasicBlock::iterator | MI, |
| int | SPAdj, | ||
| unsigned | FIOperandNum, | ||
| RegScavenger * | RS = nullptr |
||
| ) | const [pure virtual] |
eliminateFrameIndex - This method must be overriden to eliminate abstract frame indices from instructions which may use them. The instruction referenced by the iterator contains an MO_FrameIndex operand which must be eliminated by this method. This method may modify or replace the specified instruction, as long as it keeps the iterator pointing at the finished product. SPAdj is the SP adjustment due to call frame setup instruction. FIOperandNum is the FI operand number.
Referenced by llvm::RegScavenger::scavengeRegister().
| const TargetRegisterClass * TargetRegisterInfo::getAllocatableClass | ( | const TargetRegisterClass * | RC | ) | const |
getAllocatableClass - Return the maximal subclass of the given register class that is alloctable, or NULL.
Definition at line 87 of file TargetRegisterInfo.cpp.
References llvm::countTrailingZeros(), getNumRegClasses(), getRegClass(), llvm::TargetRegisterClass::getSubClassMask(), and llvm::TargetRegisterClass::isAllocatable().
Referenced by getAllocatableSet().
| BitVector TargetRegisterInfo::getAllocatableSet | ( | const MachineFunction & | MF, |
| const TargetRegisterClass * | RC = nullptr |
||
| ) | const |
getAllocatableSet - Returns a bitset indexed by register number indicating if a register is allocatable or not. If a register class is specified, returns the subset for the class.
Definition at line 138 of file TargetRegisterInfo.cpp.
References llvm::BitVector::flip(), getAllocatableClass(), getAllocatableSetForRC(), llvm::MCRegisterInfo::getNumRegs(), getReservedRegs(), I, regclass_begin(), and regclass_end().
Referenced by addLiveInRegs(), llvm::AggressiveAntiDepBreaker::AggressiveAntiDepBreaker(), and llvm::RegScavenger::scavengeRegister().
| virtual const MCPhysReg* llvm::TargetRegisterInfo::getCalleeSavedRegs | ( | const MachineFunction * | MF = nullptr | ) | const [pure virtual] |
getCalleeSavedRegs - Return a null-terminated list of all of the callee saved registers on this target. The register should be in the order of desired callee-save stack frame offset. The first register is closest to the incoming stack pointer if stack grows down, and vice versa.
Referenced by DoesModifyCalleeSavedReg(), llvm::MipsFrameLowering::estimateStackSize(), llvm::MachineFrameInfo::getPristineRegs(), llvm::SystemZFrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::RegisterClassInfo::runOnMachineFunction(), llvm::CriticalAntiDepBreaker::StartBlock(), llvm::AggressiveAntiDepBreaker::StartBlock(), and llvm::tryFoldSPUpdateIntoPushPop().
| virtual const uint32_t* llvm::TargetRegisterInfo::getCallPreservedMask | ( | CallingConv::ID | ) | const [inline, virtual] |
getCallPreservedMask - Return a mask of call-preserved registers for the given calling convention on the current sub-target. The mask should include all call-preserved aliases. This is used by the register allocator to determine which registers can be live across a call.
The mask is an array containing (TRI::getNumRegs()+31)/32 entries. A set bit indicates that all bits of the corresponding register are preserved across the function call. The bit mask is expected to be sub-register complete, i.e. if A is preserved, so are all its sub-registers.
Bits are numbered from the LSB, so the bit for physical register Reg can be found as (Mask[Reg / 32] >> Reg % 32) & 1.
A NULL pointer means that no register mask will be used, and call instructions should use implicit-def operands to indicate call clobbered registers.
Definition at line 444 of file TargetRegisterInfo.h.
Referenced by llvm::MipsTargetLowering::getOpndList(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), and llvm::FastISel::selectPatchpoint().
| const TargetRegisterClass * TargetRegisterInfo::getCommonSubClass | ( | const TargetRegisterClass * | A, |
| const TargetRegisterClass * | B | ||
| ) | const |
getCommonSubClass - find the largest common subclass of A and B. Return NULL if there is no common subclass.
Definition at line 171 of file TargetRegisterInfo.cpp.
References llvm::ARM_PROC::A, firstCommonClass(), and llvm::TargetRegisterClass::getSubClassMask().
Referenced by llvm::MachineRegisterInfo::constrainRegClass(), llvm::LiveStacks::getOrCreateInterval(), llvm::MachineInstr::getRegClassConstraintEffect(), llvm::CoalescerPair::setRegisters(), and shareSameRegisterFile().
| const TargetRegisterClass * TargetRegisterInfo::getCommonSuperRegClass | ( | const TargetRegisterClass * | RCA, |
| unsigned | SubA, | ||
| const TargetRegisterClass * | RCB, | ||
| unsigned | SubB, | ||
| unsigned & | PreA, | ||
| unsigned & | PreB | ||
| ) | const |
getCommonSuperRegClass - Find a common super-register class if it exists.
Find a register class, SuperRC and two sub-register indices, PreA and PreB, such that:
1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
SuperRC will be chosen such that no super-class of SuperRC satisfies the requirements, and there is no register class with a smaller spill size that satisfies the requirements.
SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
Either of the PreA and PreB sub-register indices may be returned as 0. In that case, the returned register class will be a sub-class of the corresponding argument register class.
The function returns NULL if no register class can be found.
Definition at line 201 of file TargetRegisterInfo.cpp.
References composeSubRegIndices(), firstCommonClass(), llvm::TargetRegisterClass::getSize(), llvm::SuperRegClassIterator::isValid(), and std::swap().
Referenced by llvm::CoalescerPair::setRegisters(), and shareSameRegisterFile().
| unsigned llvm::TargetRegisterInfo::getCostPerUse | ( | unsigned | RegNo | ) | const [inline] |
getCostPerUse - Return the additional cost of using this register instead of other registers in its class.
Definition at line 324 of file TargetRegisterInfo.h.
References llvm::TargetRegisterInfoDesc::CostPerUse.
| unsigned llvm::TargetRegisterInfo::getCoveringLanes | ( | ) | const [inline] |
The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-registers overlap - they can't be used to determine if a set of sub-registers completely cover another sub-register.
The X86 general purpose registers have two lanes corresponding to the sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have lane masks '3', but the sub_16bit sub-register doesn't fully cover the sub_32bit sub-register.
On the other hand, the ARM NEON lanes fully cover their registers: The dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes. This is related to the CoveredBySubRegs property on register definitions.
This function returns a bit mask of lanes that completely cover their sub-registers. More precisely, given:
Covering = getCoveringLanes(); MaskA = getSubRegIndexLaneMask(SubA); MaskB = getSubRegIndexLaneMask(SubB);
If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by SubB.
Definition at line 390 of file TargetRegisterInfo.h.
| virtual const TargetRegisterClass* llvm::TargetRegisterInfo::getCrossCopyRegClass | ( | const TargetRegisterClass * | RC | ) | const [inline, virtual] |
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from. If it is possible to copy the register directly without using a cross register class copy, return the specified RC. Returns NULL if it is not possible to copy between a two registers of the specified class.
Definition at line 584 of file TargetRegisterInfo.h.
| virtual unsigned llvm::TargetRegisterInfo::getCSRFirstUseCost | ( | ) | const [inline, virtual] |
Allow the target to override the cost of using a callee-saved register for the first time. Default value of 0 means we will use a callee-saved register if it is available.
Definition at line 695 of file TargetRegisterInfo.h.
| virtual int64_t llvm::TargetRegisterInfo::getFrameIndexInstrOffset | ( | const MachineInstr * | MI, |
| int | Idx | ||
| ) | const [inline, virtual] |
getFrameIndexInstrOffset - Get the offset from the referenced frame index in the instruction, if there is one.
Definition at line 749 of file TargetRegisterInfo.h.
| virtual unsigned llvm::TargetRegisterInfo::getFrameRegister | ( | const MachineFunction & | MF | ) | const [pure virtual] |
Debug information queries.
getFrameRegister - This method should return the register used as a base for values allocated in the current stack frame.
Referenced by llvm::DwarfUnit::addRegisterOffset(), llvm::MipsAsmPrinter::emitFrameDirective(), llvm::TargetFrameLowering::getFrameIndexReference(), and llvm::SelectionDAGISel::runOnMachineFunction().
| virtual const TargetRegisterClass* llvm::TargetRegisterInfo::getLargestLegalSuperClass | ( | const TargetRegisterClass * | RC | ) | const [inline, virtual] |
getLargestLegalSuperClass - Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size. The returned register class can be used to create virtual registers which means that all its registers can be copied and spilled.
The default implementation is very conservative and doesn't allow the register allocator to inflate register classes.
Definition at line 593 of file TargetRegisterInfo.h.
Referenced by llvm::MachineRegisterInfo::recomputeRegClass().
| unsigned llvm::TargetRegisterInfo::getMatchingSuperReg | ( | unsigned | Reg, |
| unsigned | SubIdx, | ||
| const TargetRegisterClass * | RC | ||
| ) | const [inline] |
getMatchingSuperReg - Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition at line 457 of file TargetRegisterInfo.h.
References llvm::TargetRegisterClass::MC.
Referenced by copyHint(), llvm::AArch64InstrInfo::copyPhysReg(), llvm::PPCInstrInfo::copyPhysReg(), emitAlignedDPRCS2Restores(), emitAlignedDPRCS2Spills(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), getCorrespondingDRegAndLane(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::PPCTargetLowering::getRegForInlineAsmConstraint(), llvm::SITargetLowering::LowerFormalArguments(), and llvm::CoalescerPair::setRegisters().
| const TargetRegisterClass * TargetRegisterInfo::getMatchingSuperRegClass | ( | const TargetRegisterClass * | A, |
| const TargetRegisterClass * | B, | ||
| unsigned | Idx | ||
| ) | const [virtual] |
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B.
TableGen will synthesize missing A sub-classes.
Definition at line 185 of file TargetRegisterInfo.cpp.
References firstCommonClass(), llvm::TargetRegisterClass::getSubClassMask(), and llvm::SuperRegClassIterator::isValid().
Referenced by llvm::MachineInstr::getRegClassConstraintEffect(), llvm::CoalescerPair::setRegisters(), and shareSameRegisterFile().
| const TargetRegisterClass * TargetRegisterInfo::getMinimalPhysRegClass | ( | unsigned | reg, |
| EVT | VT = MVT::Other |
||
| ) | const |
getMinimalPhysRegClass - Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg.
Definition at line 111 of file TargetRegisterInfo.cpp.
References llvm::TargetRegisterClass::contains(), llvm::TargetRegisterClass::hasSubClass(), llvm::TargetRegisterClass::hasType(), I, isPhysicalRegister(), llvm::MVT::Other, regclass_begin(), and regclass_end().
Referenced by CheckForPhysRegDependency(), llvm::MipsFrameLowering::estimateStackSize(), llvm::SITargetLowering::LowerFormalArguments(), llvm::XCoreFrameLowering::restoreCalleeSavedRegisters(), llvm::HexagonFrameLowering::restoreCalleeSavedRegisters(), llvm::PPCFrameLowering::restoreCalleeSavedRegisters(), llvm::X86FrameLowering::restoreCalleeSavedRegisters(), llvm::HexagonFrameLowering::spillCalleeSavedRegisters(), llvm::MipsSEFrameLowering::spillCalleeSavedRegisters(), llvm::XCoreFrameLowering::spillCalleeSavedRegisters(), llvm::PPCFrameLowering::spillCalleeSavedRegisters(), and llvm::X86FrameLowering::spillCalleeSavedRegisters().
| unsigned llvm::TargetRegisterInfo::getNumRegClasses | ( | ) | const [inline] |
Reimplemented from llvm::MCRegisterInfo.
Definition at line 553 of file TargetRegisterInfo.h.
References regclass_begin(), and regclass_end().
Referenced by llvm::TargetLoweringBase::findRepresentativeClass(), firstCommonClass(), getAllocatableClass(), getRegClass(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), and llvm::RegisterClassInfo::runOnMachineFunction().
| virtual unsigned llvm::TargetRegisterInfo::getNumRegPressureSets | ( | ) | const [pure virtual] |
Get the number of dimensions of register pressure.
Referenced by llvm::RegPressureTracker::init(), llvm::RegPressureTracker::initLiveThru(), and llvm::RegisterClassInfo::runOnMachineFunction().
| virtual const TargetRegisterClass* llvm::TargetRegisterInfo::getPointerRegClass | ( | const MachineFunction & | MF, |
| unsigned | Kind = 0 |
||
| ) | const [inline, virtual] |
getPointerRegClass - Returns a TargetRegisterClass used for pointer values. If a target supports multiple different pointer register classes, kind specifies which one is indicated.
Definition at line 574 of file TargetRegisterInfo.h.
References llvm_unreachable.
Referenced by llvm::TargetInstrInfo::getRegClass(), and llvm::MachineInstr::getRegClassConstraint().
| void TargetRegisterInfo::getRegAllocationHints | ( | unsigned | VirtReg, |
| ArrayRef< MCPhysReg > | Order, | ||
| SmallVectorImpl< MCPhysReg > & | Hints, | ||
| const MachineFunction & | MF, | ||
| const VirtRegMap * | VRM = nullptr |
||
| ) | const [virtual] |
Get a list of 'hint' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg. These registers are effectively moved to the front of the allocation order.
The Order argument is the allocation order for VirtReg's register class as returned from RegisterClassInfo::getOrder(). The hint registers must come from Order, and they must not be reserved.
The default implementation of this function can resolve target-independent hints provided to MRI::setRegAllocationHint with HintType == 0. Targets that override this function should defer to the default implementation if they have no reason to change the allocation order for VirtReg. There may be target-independent hints.
Definition at line 264 of file TargetRegisterInfo.cpp.
References llvm::ArrayRef< T >::begin(), llvm::ArrayRef< T >::end(), llvm::VirtRegMap::getPhys(), llvm::MachineRegisterInfo::getRegAllocationHint(), llvm::MachineFunction::getRegInfo(), Hint(), isPhysicalRegister(), llvm::MachineRegisterInfo::isReserved(), isVirtualRegister(), and llvm::SmallVectorTemplateBase< T, isPodLike >::push_back().
Referenced by llvm::AllocationOrder::AllocationOrder().
| const TargetRegisterClass* llvm::TargetRegisterInfo::getRegClass | ( | unsigned | i | ) | const [inline] |
getRegClass - Returns the register class associated with the enumeration value. See class MCOperandInfo.
Reimplemented from llvm::MCRegisterInfo.
Definition at line 559 of file TargetRegisterInfo.h.
References getNumRegClasses().
Referenced by llvm::TargetLoweringBase::findRepresentativeClass(), firstCommonClass(), getAllocatableClass(), GetCostForDef(), llvm::TargetInstrInfo::getRegClass(), llvm::MachineInstr::getRegClassConstraint(), and llvm::MachineInstr::print().
| virtual const int* llvm::TargetRegisterInfo::getRegClassPressureSets | ( | const TargetRegisterClass * | RC | ) | const [pure virtual] |
Get the dimensions of register pressure impacted by this register class. Returns a -1 terminated array of pressure set IDs.
Referenced by llvm::RegisterClassInfo::computePSetLimit(), and llvm::PSetIterator::PSetIterator().
| virtual const RegClassWeight& llvm::TargetRegisterInfo::getRegClassWeight | ( | const TargetRegisterClass * | RC | ) | const [pure virtual] |
Get the weight in units of pressure for this register class.
Referenced by llvm::RegisterClassInfo::computePSetLimit(), llvm::PSetIterator::PSetIterator(), and llvm::ARMBaseRegisterInfo::shouldCoalesce().
| virtual unsigned llvm::TargetRegisterInfo::getRegPressureLimit | ( | const TargetRegisterClass * | RC, |
| MachineFunction & | MF | ||
| ) | const [inline, virtual] |
getRegPressureLimit - Return the register pressure "high water mark" for the specific register class. The scheduler is in high register pressure mode (for the specific register class) if it goes over the limit.
Note: this is the old register pressure model that relies on a manually specified representative register class per value type.
Definition at line 605 of file TargetRegisterInfo.h.
Referenced by llvm::ResourcePriorityQueue::ResourcePriorityQueue().
| virtual unsigned llvm::TargetRegisterInfo::getRegPressureSetLimit | ( | unsigned | Idx | ) | const [pure virtual] |
Get the register unit pressure limit for this dimension. This limit must be adjusted dynamically for reserved registers.
Referenced by llvm::RegisterClassInfo::computePSetLimit().
| virtual const char* llvm::TargetRegisterInfo::getRegPressureSetName | ( | unsigned | Idx | ) | const [pure virtual] |
Get the name of this register unit pressure set.
Referenced by llvm::dumpRegSetPressure(), llvm::RegPressureTracker::getMaxUpwardPressureDelta(), llvm::ScheduleDAGMILive::initRegPressure(), llvm::ConvergingVLIWScheduler::traceCandidate(), llvm::GenericSchedulerBase::traceCandidate(), llvm::GenericScheduler::tryCandidate(), and llvm::ScheduleDAGMILive::updateScheduledPressure().
| virtual const int* llvm::TargetRegisterInfo::getRegUnitPressureSets | ( | unsigned | RegUnit | ) | const [pure virtual] |
Get the dimensions of register pressure impacted by this register unit. Returns a -1 terminated array of pressure set IDs.
Referenced by llvm::PSetIterator::PSetIterator().
| virtual unsigned llvm::TargetRegisterInfo::getRegUnitWeight | ( | unsigned | RegUnit | ) | const [pure virtual] |
Get the weight in units of pressure for this register unit.
Referenced by llvm::PSetIterator::PSetIterator().
| virtual BitVector llvm::TargetRegisterInfo::getReservedRegs | ( | const MachineFunction & | MF | ) | const [pure virtual] |
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times, e.g. SP, RA. This is used by register scavenger to determine what registers are free.
Referenced by llvm::MachineRegisterInfo::freezeReservedRegs(), and getAllocatableSet().
| virtual const TargetRegisterClass* llvm::TargetRegisterInfo::getSubClassWithSubReg | ( | const TargetRegisterClass * | RC, |
| unsigned | Idx | ||
| ) | const [inline, virtual] |
getSubClassWithSubReg - Returns the largest legal sub-class of RC that supports the sub-register index Idx. If no such sub-class exists, return NULL. If all registers in RC already have an Idx sub-register, return RC.
TableGen generates a version of this function that is good enough in most cases. Targets can override if they have constraints that TableGen doesn't understand. For example, the x86 sub_8bit sub-register index is supported by the full GR32 register class in 64-bit mode, but only by the GR32_ABCD regiister class in 32-bit mode.
TableGen will synthesize missing RC sub-classes.
Definition at line 484 of file TargetRegisterInfo.h.
Referenced by llvm::FastISel::fastEmitInst_extractsubreg(), and llvm::MachineInstr::getRegClassConstraintEffect().
| unsigned llvm::TargetRegisterInfo::getSubRegIndexLaneMask | ( | unsigned | SubIdx | ) | const [inline] |
getSubRegIndexLaneMask - Return a bitmask representing the parts of a register that are covered by SubIdx.
Lane masks for sub-register indices are similar to register units for physical registers. The individual bits in a lane mask can't be assigned any specific meaning. They can be used to check if two sub-register indices overlap.
If the target has a register such that:
getSubReg(Reg, A) overlaps getSubReg(Reg, B)
then:
getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B) != 0
The converse is not necessarily true. If two lane masks have a common bit, the corresponding sub-registers may not overlap, but it can be assumed that they usually will.
Definition at line 361 of file TargetRegisterInfo.h.
References llvm::MCRegisterInfo::getNumSubRegIndices().
| const char* llvm::TargetRegisterInfo::getSubRegIndexName | ( | unsigned | SubIdx | ) | const [inline] |
getSubRegIndexName - Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Definition at line 336 of file TargetRegisterInfo.h.
References llvm::MCRegisterInfo::getNumSubRegIndices().
Referenced by llvm::PrintReg::print(), and llvm::MachineInstr::print().
| bool llvm::TargetRegisterInfo::hasRegUnit | ( | unsigned | Reg, |
| unsigned | RegUnit | ||
| ) | const [inline] |
hasRegUnit - Returns true if Reg contains RegUnit.
Definition at line 411 of file TargetRegisterInfo.h.
References llvm::MCRegisterInfo::DiffListIterator::isValid().
| virtual bool llvm::TargetRegisterInfo::hasReservedSpillSlot | ( | const MachineFunction & | MF, |
| unsigned | Reg, | ||
| int & | FrameIdx | ||
| ) | const [inline, virtual] |
hasReservedSpillSlot - Return true if target has reserved a spill slot in the stack frame of the given function for the specified register. e.g. On x86, if the frame register is required, the first fixed stack object is reserved as its spill slot. This tells PEI not to create a new stack frame object for the given register. It should be called only after processFunctionBeforeCalleeSavedScan().
Definition at line 729 of file TargetRegisterInfo.h.
| static unsigned llvm::TargetRegisterInfo::index2StackSlot | ( | int | FI | ) | [inline, static] |
index2StackSlot - Convert a non-negative frame index to a stack slot register value.
Definition at line 273 of file TargetRegisterInfo.h.
Referenced by llvm::LiveStacks::getOrCreateInterval().
| static unsigned llvm::TargetRegisterInfo::index2VirtReg | ( | unsigned | Index | ) | [inline, static] |
index2VirtReg - Convert a 0-based index to a virtual register number. This is the inverse operation of VirtReg2IndexFunctor below.
Definition at line 301 of file TargetRegisterInfo.h.
Referenced by llvm::LiveIntervals::addKillFlags(), llvm::LiveVariables::addNewBlock(), llvm::calculateSpillWeightsAndHints(), llvm::MachineRegisterInfo::clearVirtRegs(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::VirtRegMap::print(), llvm::LiveIntervals::print(), llvm::LiveIntervals::releaseMemory(), llvm::LiveVariables::runOnMachineFunction(), llvm::MachineBasicBlock::SplitCriticalEdge(), and llvm::MachineRegisterInfo::verifyUseLists().
| virtual bool llvm::TargetRegisterInfo::isFrameOffsetLegal | ( | const MachineInstr * | MI, |
| int64_t | Offset | ||
| ) | const [inline, virtual] |
isFrameOffsetLegal - Determine whether a given offset immediate is encodable to resolve a frame index.
Definition at line 780 of file TargetRegisterInfo.h.
References llvm_unreachable.
Referenced by lookupCandidateBaseReg().
| bool llvm::TargetRegisterInfo::isInAllocatableClass | ( | unsigned | RegNo | ) | const [inline] |
isInAllocatableClass - Return true if the register is in the allocation of any register class.
Definition at line 330 of file TargetRegisterInfo.h.
References llvm::TargetRegisterInfoDesc::inAllocatableClass.
Referenced by llvm::MachineRegisterInfo::isAllocatable().
| static bool llvm::TargetRegisterInfo::isPhysicalRegister | ( | unsigned | Reg | ) | [inline, static] |
isPhysicalRegister - Return true if the specified register number is in the physical register namespace.
Definition at line 280 of file TargetRegisterInfo.h.
References isStackSlot().
Referenced by llvm::ARMBaseInstrInfo::AddDReg(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstr::addRegisterDead(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineInstr::addRegisterKilled(), llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), AddSubReg(), llvm::MachineOperandIteratorBase::analyzePhysReg(), llvm::VirtRegMap::assignVirt2Phys(), biasPhysRegCopy(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::VirtRegAuxInfo::calculateSpillWeightAndHint(), canCompareBeNewValueJump(), canFoldCopy(), canFoldIntoMOVCC(), llvm::MachineInstr::clearRegisterKills(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), countOperands(), findOnlyInterestingUse(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::CoalescerPair::flip(), getDataDeps(), getDef(), llvm::RegisterClassInfo::getLastCalleeSavedAlias(), getMappedReg(), getMinimalPhysRegClass(), getRegAllocationHints(), llvm::VirtRegMap::hasKnownPreference(), INITIALIZE_PASS(), llvm::CoalescerPair::isCoalescable(), llvm::MachineRegisterInfo::isConstantPhysReg(), isCopyToReg(), isEvenReg(), llvm::MachineInstr::isIdenticalTo(), isKilled(), isLocalCopy(), llvm::Thumb1InstrInfo::loadRegFromStackSlot(), llvm::Thumb2InstrInfo::loadRegFromStackSlot(), llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), MIIsInTerminatorSequence(), llvm::MachineInstr::print(), llvm::ARMAsmPrinter::printOperand(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::GenericScheduler::reschedulePhysRegCopies(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::MachineInstr::setPhysRegsDeadExcept(), llvm::CoalescerPair::setRegisters(), llvm::MachineBasicBlock::SplitCriticalEdge(), llvm::Thumb1InstrInfo::storeRegToStackSlot(), llvm::MachineInstr::substituteRegister(), llvm::MachineOperand::substPhysReg(), UpdateOperandRegClass(), updatePhysDepsDownwards(), and updatePhysDepsUpwards().
| static bool llvm::TargetRegisterInfo::isStackSlot | ( | unsigned | Reg | ) | [inline, static] |
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable that normally holds a register. isStackSlot() returns true if Reg is in the range used for stack slots.
Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack slots, so if a variable may contains a stack slot, always check isStackSlot() first.
Definition at line 260 of file TargetRegisterInfo.h.
Referenced by isPhysicalRegister(), isVirtualRegister(), llvm::PrintReg::print(), and stackSlot2Index().
| static bool llvm::TargetRegisterInfo::isVirtualRegister | ( | unsigned | Reg | ) | [inline, static] |
isVirtualRegister - Return true if the specified register number is in the virtual register namespace.
Definition at line 287 of file TargetRegisterInfo.h.
References isStackSlot().
Referenced by llvm::LiveVariables::addNewBlock(), llvm::RegPressureTracker::advance(), llvm::RegAllocBase::allocatePhysRegs(), llvm::VirtRegMap::assignVirt2Phys(), llvm::VirtRegMap::assignVirt2StackSlot(), llvm::RegPressureTracker::bumpDownwardPressure(), canCombineWithMUL(), canFoldCopy(), canFoldIntoCSel(), canFoldIntoMOVCC(), CheckForPhysRegDependency(), llvm::VirtRegMap::clearVirt(), llvm::ScheduleDAGMILive::computeCyclicCriticalPath(), llvm::ScheduleDAGSDNodes::computeOperandLatency(), llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(), llvm::FastISel::constrainOperandRegClass(), llvm::LiveRegSet::contains(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), copyHint(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::LiveRegSet::erase(), llvm::MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval(), llvm::FastISel::fastEmitInst_extractsubreg(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::RegScavenger::forward(), genMadd(), genMaddR(), getCallTargetRegOpnd(), llvm::MachineInstrExpressionTrait::getHashValue(), llvm::AMDGPUInstrInfo::getIndirectIndexBegin(), llvm::RegPressureTracker::getLiveRange(), getMappedReg(), llvm::PPCInstrInfo::getOperandLatency(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::VirtRegMap::getPhys(), llvm::SIRegisterInfo::getPhysRegClass(), getRegAllocationHints(), llvm::VirtRegMap::getStackSlot(), llvm::LiveVariables::getVarInfo(), llvm::VirtRegMap::hasKnownPreference(), hasOnlyLiveInOpers(), hasOnlyLiveOutUses(), llvm::VirtRegMap::hasPreferredPhys(), hasVGPROperands(), INITIALIZE_PASS(), llvm::RegPressureTracker::initLiveThru(), llvm::LiveRegSet::insert(), isFPR64(), isGPR64(), llvm::R600InstrInfo::isLegalToSplitMBBAt(), isPhysicalRegCopy(), llvm::R600RegisterInfo::isPhysRegLiveAcrossClauses(), isPlainlyKilled(), isVGPR(), llvm::SIInstrInfo::legalizeOperands(), llvm::Mips16InstrInfo::loadImmediate(), llvm::AArch64InstrInfo::loadRegFromStackSlot(), MatchingStackOffset(), llvm::PrintReg::print(), llvm::PrintVRegOrUnit::print(), llvm::MachineInstr::print(), llvm::ARMBaseInstrInfo::produceSameValue(), llvm::PSetIterator::PSetIterator(), RegisterOperands::pushRegUnits(), llvm::R600InstrInfo::readsLDSSrcReg(), llvm::RegPressureTracker::recede(), regsOverlap(), removeCopies(), llvm::LiveVariables::removeVirtualRegistersKilled(), llvm::LiveIntervals::repairIntervalsInRange(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::Thumb1RegisterInfo::saveScavengerRegister(), llvm::RegScavenger::scavengeRegister(), llvm::CoalescerPair::setRegisters(), llvm::LiveIntervals::shrinkToUses(), llvm::MachineBasicBlock::SplitCriticalEdge(), llvm::AArch64InstrInfo::storeRegToStackSlot(), llvm::MachineOperand::substVirtReg(), llvm::LiveIntervals::HMEditor::updateAllRanges(), llvm::ScheduleDAGMILive::updatePressureDiffs(), llvm::ARMBaseRegisterInfo::UpdateRegAllocHint(), llvm::SIInstrInfo::verifyInstruction(), and virtReg2Index().
| virtual void llvm::TargetRegisterInfo::materializeFrameBaseRegister | ( | MachineBasicBlock * | MBB, |
| unsigned | BaseReg, | ||
| int | FrameIdx, | ||
| int64_t | Offset | ||
| ) | const [inline, virtual] |
materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx before insertion point I.
Definition at line 764 of file TargetRegisterInfo.h.
References llvm_unreachable.
| virtual bool llvm::TargetRegisterInfo::mayOverrideLocalAssignment | ( | ) | const [inline, virtual] |
Allow the target to override register assignment heuristics based on the live range size. If this returns false, then local live ranges are always assigned in order regardless of their size. This is a temporary hook for debugging downstream codegen failures exposed by regalloc.
Definition at line 690 of file TargetRegisterInfo.h.
| virtual bool llvm::TargetRegisterInfo::needsFrameBaseReg | ( | MachineInstr * | MI, |
| int64_t | Offset | ||
| ) | const [inline, virtual] |
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP. Used by LocalStackFrameAllocation to determine which frame index references it should create new base registers for.
Definition at line 758 of file TargetRegisterInfo.h.
| virtual bool llvm::TargetRegisterInfo::needsStackRealignment | ( | const MachineFunction & | MF | ) | const [inline, virtual] |
needsStackRealignment - true if storage within the function requires the stack pointer to be aligned more than the normal calling convention calls for.
Definition at line 743 of file TargetRegisterInfo.h.
Referenced by llvm::MachineFrameInfo::estimateStackSize(), getMemcpyLoadsAndStores(), llvm::ARMFrameLowering::hasFP(), llvm::AArch64FrameLowering::hasFP(), and llvm::X86FrameLowering::hasFP().
| regclass_iterator llvm::TargetRegisterInfo::regclass_begin | ( | ) | const [inline] |
Register class iterators
Reimplemented from llvm::MCRegisterInfo.
Definition at line 550 of file TargetRegisterInfo.h.
Referenced by llvm::RegisterClassInfo::computePSetLimit(), getAllocatableSet(), getMinimalPhysRegClass(), getNumRegClasses(), llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::ResourcePriorityQueue::regPressureDelta(), and llvm::ResourcePriorityQueue::ResourcePriorityQueue().
| regclass_iterator llvm::TargetRegisterInfo::regclass_end | ( | ) | const [inline] |
Reimplemented from llvm::MCRegisterInfo.
Definition at line 551 of file TargetRegisterInfo.h.
Referenced by llvm::RegisterClassInfo::computePSetLimit(), getAllocatableSet(), getMinimalPhysRegClass(), getNumRegClasses(), llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::ResourcePriorityQueue::regPressureDelta(), and llvm::ResourcePriorityQueue::ResourcePriorityQueue().
| bool llvm::TargetRegisterInfo::regsOverlap | ( | unsigned | regA, |
| unsigned | regB | ||
| ) | const [inline] |
regsOverlap - Returns true if the two registers are equal or alias each other. The registers may be virtual register.
Definition at line 394 of file TargetRegisterInfo.h.
References llvm::MCRegisterInfo::DiffListIterator::isValid(), and isVirtualRegister().
Referenced by llvm::MachineOperandIteratorBase::analyzePhysReg(), llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), canClobberPhysRegDefs(), canClobberReachingPhysRegUse(), llvm::ARMBaseInstrInfo::copyPhysReg(), llvm::MachineInstr::findRegisterDefOperandIdx(), IsSafeAndProfitableToMove(), regsAreCompatible(), and llvm::MachineInstr::setPhysRegsDeadExcept().
| virtual bool llvm::TargetRegisterInfo::requiresFrameIndexScavenging | ( | const MachineFunction & | MF | ) | const [inline, virtual] |
requiresFrameIndexScavenging - returns true if the target requires post PEI scavenging of registers for materializing frame index constants.
Definition at line 712 of file TargetRegisterInfo.h.
Referenced by llvm::PEI::runOnMachineFunction().
| virtual bool llvm::TargetRegisterInfo::requiresRegisterScavenging | ( | const MachineFunction & | MF | ) | const [inline, virtual] |
requiresRegisterScavenging - returns true if the target requires (and can make use of) the register scavenger.
Definition at line 699 of file TargetRegisterInfo.h.
Referenced by llvm::PEI::runOnMachineFunction().
| virtual bool llvm::TargetRegisterInfo::requiresVirtualBaseRegisters | ( | const MachineFunction & | MF | ) | const [inline, virtual] |
requiresVirtualBaseRegisters - Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access.
Definition at line 719 of file TargetRegisterInfo.h.
| virtual void llvm::TargetRegisterInfo::resolveFrameIndex | ( | MachineInstr & | MI, |
| unsigned | BaseReg, | ||
| int64_t | Offset | ||
| ) | const [inline, virtual] |
resolveFrameIndex - Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead.
Definition at line 773 of file TargetRegisterInfo.h.
References llvm_unreachable.
| virtual bool llvm::TargetRegisterInfo::reverseLocalAssignment | ( | ) | const [inline, virtual] |
Allow the target to reverse allocation order of local live ranges. This will generally allocate shorter local live ranges first. For targets with many registers, this could reduce regalloc compile time by a large factor. It is disabled by default for three reasons: (1) Top-down allocation is simpler and easier to debug for targets that don't benefit from reversing the order. (2) Bottom-up allocation could result in poor evicition decisions on some targets affecting the performance of compiled code. (3) Bottom-up allocation is no longer guaranteed to optimally color.
Definition at line 684 of file TargetRegisterInfo.h.
| virtual bool llvm::TargetRegisterInfo::saveScavengerRegister | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| MachineBasicBlock::iterator & | UseMI, | ||
| const TargetRegisterClass * | RC, | ||
| unsigned | Reg | ||
| ) | const [inline, virtual] |
saveScavengerRegister - Spill the register so it can be used by the register scavenger. Return true if the register was spilled, false otherwise. If this function does not spill the register, the scavenger will instead spill it to the emergency spill slot.
Definition at line 791 of file TargetRegisterInfo.h.
Referenced by llvm::RegScavenger::scavengeRegister().
| virtual bool llvm::TargetRegisterInfo::shouldCoalesce | ( | MachineInstr * | MI, |
| const TargetRegisterClass * | SrcRC, | ||
| unsigned | SubReg, | ||
| const TargetRegisterClass * | DstRC, | ||
| unsigned | DstSubReg, | ||
| const TargetRegisterClass * | NewRC | ||
| ) | const [inline, virtual] |
Subtarget Hooks.
SrcRC and DstRC will be morphed into NewRC if this returns true.
Definition at line 814 of file TargetRegisterInfo.h.
| static int llvm::TargetRegisterInfo::stackSlot2Index | ( | unsigned | Reg | ) | [inline, static] |
stackSlot2Index - Compute the frame index from a register value representing a stack slot.
Definition at line 266 of file TargetRegisterInfo.h.
References isStackSlot().
Referenced by llvm::PrintReg::print().
| virtual bool llvm::TargetRegisterInfo::trackLivenessAfterRegAlloc | ( | const MachineFunction & | MF | ) | const [inline, virtual] |
trackLivenessAfterRegAlloc - returns true if the live-ins should be tracked after register allocation.
Definition at line 736 of file TargetRegisterInfo.h.
Referenced by llvm::BranchFolder::OptimizeFunction().
| virtual void llvm::TargetRegisterInfo::UpdateRegAllocHint | ( | unsigned | Reg, |
| unsigned | NewReg, | ||
| MachineFunction & | MF | ||
| ) | const [inline, virtual] |
UpdateRegAllocHint - A callback to allow target a chance to update register allocation hints when a register is "changed" (e.g. coalesced) to another register. e.g. On ARM, some virtual registers should target register pairs, if one of pair is coalesced to another register, the allocation hint of the other half of the pair should be changed to point to the new register.
Definition at line 670 of file TargetRegisterInfo.h.
| virtual bool llvm::TargetRegisterInfo::useFPForScavengingIndex | ( | const MachineFunction & | MF | ) | const [inline, virtual] |
useFPForScavengingIndex - returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot.
Definition at line 706 of file TargetRegisterInfo.h.
| static unsigned llvm::TargetRegisterInfo::virtReg2Index | ( | unsigned | Reg | ) | [inline, static] |
virtReg2Index - Convert a virtual register number to a 0-based index. The first virtual register in a function will get the index 0.
Definition at line 294 of file TargetRegisterInfo.h.
References isVirtualRegister().
Referenced by llvm::VReg2SUnit::getSparseSetIndex(), llvm::VirtReg2IndexFunctor::operator()(), llvm::PrintReg::print(), llvm::PrintVRegOrUnit::print(), and llvm::SelectionDAGISel::runOnMachineFunction().
The documentation for this class was generated from the following files:
1.7.6.1