#include "llvm/MC/MCRegisterInfo.h"

Include dependency graph for R600Defines.h:

This graph shows which files directly or indirectly include this file:

Namespaces
namespace	R600_InstFlag
namespace	OpName
Defines
#define	MO_FLAG_CLAMP (1 << 0)
#define	MO_FLAG_NEG (1 << 1)
#define	MO_FLAG_ABS (1 << 2)
#define	MO_FLAG_MASK (1 << 3)
#define	MO_FLAG_PUSH (1 << 4)
#define	MO_FLAG_NOT_LAST (1 << 5)
#define	MO_FLAG_LAST (1 << 6)
#define	NUM_MO_FLAGS 7
#define	GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3)
	Helper for getting the operand index for the instruction flags operand.
#define	HAS_NATIVE_OPERANDS(Flags) ((Flags) & R600_InstFlag::NATIVE_OPERANDS)
#define	HW_REG_MASK 0x1ff
	Defines for extracting register information from register encoding.
#define	HW_CHAN_SHIFT 9
#define	GET_REG_CHAN(reg) ((reg) >> HW_CHAN_SHIFT)
#define	GET_REG_INDEX(reg) ((reg) & HW_REG_MASK)
#define	IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
#define	IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
#define	R_02880C_DB_SHADER_CONTROL 0x02880C
#define	S_02880C_KILL_ENABLE(x) (((x) & 0x1) << 6)
#define	S_NUM_GPRS(x) (((x) & 0xFF) << 0)
#define	S_STACK_SIZE(x) (((x) & 0xFF) << 8)
#define	R_028850_SQ_PGM_RESOURCES_PS 0x028850
#define	R_028868_SQ_PGM_RESOURCES_VS 0x028868
#define	R_028844_SQ_PGM_RESOURCES_PS 0x028844
#define	R_028860_SQ_PGM_RESOURCES_VS 0x028860
#define	R_028878_SQ_PGM_RESOURCES_GS 0x028878
#define	R_0288D4_SQ_PGM_RESOURCES_LS 0x0288d4
#define	R_0288E8_SQ_LDS_ALLOC 0x0288E8
Enumerations
enum	R600_InstFlag::TIF { R600_InstFlag::TRANS_ONLY = (1 << 0), R600_InstFlag::TEX = (1 << 1), R600_InstFlag::REDUCTION = (1 << 2), R600_InstFlag::FC = (1 << 3), R600_InstFlag::TRIG = (1 << 4), R600_InstFlag::OP3 = (1 << 5), R600_InstFlag::VECTOR = (1 << 6), R600_InstFlag::NATIVE_OPERANDS = (1 << 9), R600_InstFlag::OP1 = (1 << 10), R600_InstFlag::OP2 = (1 << 11), R600_InstFlag::VTX_INST = (1 << 12), R600_InstFlag::TEX_INST = (1 << 13), R600_InstFlag::ALU_INST = (1 << 14), R600_InstFlag::LDS_1A = (1 << 15), R600_InstFlag::LDS_1A1D = (1 << 16), R600_InstFlag::IS_EXPORT = (1 << 17), R600_InstFlag::LDS_1A2D = (1 << 18) }
enum	OpName::VecOps { OpName::UPDATE_EXEC_MASK_X, OpName::UPDATE_PREDICATE_X, OpName::WRITE_X, OpName::OMOD_X, OpName::DST_REL_X, OpName::CLAMP_X, OpName::SRC0_X, OpName::SRC0_NEG_X, OpName::SRC0_REL_X, OpName::SRC0_ABS_X, OpName::SRC0_SEL_X, OpName::SRC1_X, OpName::SRC1_NEG_X, OpName::SRC1_REL_X, OpName::SRC1_ABS_X, OpName::SRC1_SEL_X, OpName::PRED_SEL_X, OpName::UPDATE_EXEC_MASK_Y, OpName::UPDATE_PREDICATE_Y, OpName::WRITE_Y, OpName::OMOD_Y, OpName::DST_REL_Y, OpName::CLAMP_Y, OpName::SRC0_Y, OpName::SRC0_NEG_Y, OpName::SRC0_REL_Y, OpName::SRC0_ABS_Y, OpName::SRC0_SEL_Y, OpName::SRC1_Y, OpName::SRC1_NEG_Y, OpName::SRC1_REL_Y, OpName::SRC1_ABS_Y, OpName::SRC1_SEL_Y, OpName::PRED_SEL_Y, OpName::UPDATE_EXEC_MASK_Z, OpName::UPDATE_PREDICATE_Z, OpName::WRITE_Z, OpName::OMOD_Z, OpName::DST_REL_Z, OpName::CLAMP_Z, OpName::SRC0_Z, OpName::SRC0_NEG_Z, OpName::SRC0_REL_Z, OpName::SRC0_ABS_Z, OpName::SRC0_SEL_Z, OpName::SRC1_Z, OpName::SRC1_NEG_Z, OpName::SRC1_REL_Z, OpName::SRC1_ABS_Z, OpName::SRC1_SEL_Z, OpName::PRED_SEL_Z, OpName::UPDATE_EXEC_MASK_W, OpName::UPDATE_PREDICATE_W, OpName::WRITE_W, OpName::OMOD_W, OpName::DST_REL_W, OpName::CLAMP_W, OpName::SRC0_W, OpName::SRC0_NEG_W, OpName::SRC0_REL_W, OpName::SRC0_ABS_W, OpName::SRC0_SEL_W, OpName::SRC1_W, OpName::SRC1_NEG_W, OpName::SRC1_REL_W, OpName::SRC1_ABS_W, OpName::SRC1_SEL_W, OpName::PRED_SEL_W, OpName::IMM_0, OpName::IMM_1, OpName::VEC_COUNT }