LLVM API Documentation
| addLoc(const CCValAssign &V) | llvm::Hexagon_CCState | [inline] |
| AllocateReg(unsigned Reg) | llvm::Hexagon_CCState | [inline] |
| AllocateReg(unsigned Reg, unsigned ShadowReg) | llvm::Hexagon_CCState | [inline] |
| AllocateReg(const unsigned *Regs, unsigned NumRegs) | llvm::Hexagon_CCState | [inline] |
| AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, unsigned NumRegs) | llvm::Hexagon_CCState | [inline] |
| AllocateStack(unsigned Size, unsigned Align) | llvm::Hexagon_CCState | [inline] |
| AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, Hexagon_CCAssignFn Fn, int NonVarArgsParams, unsigned SretValueSize) | llvm::Hexagon_CCState | |
| AnalyzeCallOperands(SmallVectorImpl< EVT > &ArgVTs, SmallVectorImpl< ISD::ArgFlagsTy > &Flags, Hexagon_CCAssignFn Fn) | llvm::Hexagon_CCState | |
| AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, Hexagon_CCAssignFn Fn, unsigned SretValueInRegs) | llvm::Hexagon_CCState | |
| AnalyzeCallResult(EVT VT, Hexagon_CCAssignFn Fn) | llvm::Hexagon_CCState | |
| AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, Hexagon_CCAssignFn Fn, unsigned SretValueInRegs) | llvm::Hexagon_CCState | |
| AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, Hexagon_CCAssignFn Fn, unsigned SretValueInRegs) | llvm::Hexagon_CCState | |
| getCallingConv() const | llvm::Hexagon_CCState | [inline] |
| getContext() const | llvm::Hexagon_CCState | [inline] |
| getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const | llvm::Hexagon_CCState | [inline] |
| getNextStackOffset() const | llvm::Hexagon_CCState | [inline] |
| getTarget() const | llvm::Hexagon_CCState | [inline] |
| HandleByVal(unsigned ValNo, EVT ValVT, EVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags) | llvm::Hexagon_CCState | |
| Hexagon_CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &TM, SmallVectorImpl< CCValAssign > &locs, LLVMContext &c) | llvm::Hexagon_CCState | |
| isAllocated(unsigned Reg) const | llvm::Hexagon_CCState | [inline] |
| isVarArg() const | llvm::Hexagon_CCState | [inline] |