LLVM API Documentation
AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override | llvm::MipsInstrInfo | |
AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify, SmallVectorImpl< MachineInstr * > &BranchInstrs) const | llvm::MipsInstrInfo | |
BranchType enum name | llvm::MipsInstrInfo | |
BT_Cond enum value | llvm::MipsInstrInfo | |
BT_CondUncond enum value | llvm::MipsInstrInfo | |
BT_Indirect enum value | llvm::MipsInstrInfo | |
BT_NoBranch enum value | llvm::MipsInstrInfo | |
BT_None enum value | llvm::MipsInstrInfo | |
BT_Uncond enum value | llvm::MipsInstrInfo | |
create(MipsSubtarget &STI) | llvm::MipsInstrInfo | [static] |
genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const | llvm::MipsInstrInfo | |
GetInstSizeInBytes(const MachineInstr *MI) const | llvm::MipsInstrInfo | |
GetMemOperand(MachineBasicBlock &MBB, int FI, unsigned Flag) const | llvm::MipsInstrInfo | [protected] |
getOppositeBranchOpc(unsigned Opc) const =0 | llvm::MipsInstrInfo | [pure virtual] |
getRegisterInfo() const =0 | llvm::MipsInstrInfo | [pure virtual] |
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl< MachineOperand > &Cond, DebugLoc DL) const override | llvm::MipsInstrInfo | |
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override | llvm::MipsInstrInfo | |
isZeroImm(const MachineOperand &op) const | llvm::MipsInstrInfo | [protected] |
loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0 | llvm::MipsInstrInfo | [pure virtual] |
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override | llvm::MipsInstrInfo | [inline] |
MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc) | llvm::MipsInstrInfo | [explicit] |
RemoveBranch(MachineBasicBlock &MBB) const override | llvm::MipsInstrInfo | |
ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override | llvm::MipsInstrInfo | |
storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0 | llvm::MipsInstrInfo | [pure virtual] |
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override | llvm::MipsInstrInfo | [inline] |
Subtarget | llvm::MipsInstrInfo | [protected] |
UncondBrOpc | llvm::MipsInstrInfo | [protected] |