Here is a brief summary of how to invoke as. For details, Chapter 3 Command-Line Options.
as [-a[cdhlns][=file]] [--alternate] [-D]
[--defsym sym=val] [-f] [-g] [--gstabs] [--gstabs+]
[--gdwarf-2] [--help] [-I dir] [-J] [-K] [-L]
[--listing-lhs-width=NUM] [--listing-lhs-width2=NUM]
[--listing-rhs-width=NUM] [--listing-cont-lines=NUM]
[--keep-locals] [-o objfile] [-R] [--statistics] [-v]
[-version] [--version] [-W] [--warn] [--fatal-warnings]
[-w] [-x] [-Z] [--target-help] [target-options]
[--|files …]
Target Alpha options:
[-mcpu]
[-mdebug | -no-mdebug]
[-relax] [-g] [-Gsize]
[-F] [-32addr]
Target ARC options:
[-marc[5|6|7|8]]
[-EB|-EL]
Target ARM options:
[-mcpu=processor[+extension…]]
[-march=architecture[+extension…]]
[-mfpu=floating-point-format]
[-mfloat-abi=abi]
[-meabi=ver]
[-mthumb]
[-EB|-EL]
[-mapcs-32|-mapcs-26|-mapcs-float|
-mapcs-reentrant]
[-mthumb-interwork] [-moabi] [-k]
Target CRIS options:
[--underscore | --no-underscore]
[--pic] [-N]
[--emulation=criself | --emulation=crisaout]
Target D10V options:
[-O]
Target D30V options:
[-O|-n|-N]
Target i386 options:
[--32|--64] [-n]
Target i960 options:
[-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB|
-AKC|-AMC]
[-b] [-no-relax]
Target IP2K options:
[-mip2022|-mip2022ext]
Target M32R options:
[--m32rx|--[no-]warn-explicit-parallel-conflicts|
--W[n]p]
Target M680X0 options:
[-l] [-m68000|-m68010|-m68020|…]
Target M68HC11 options:
[-m68hc11|-m68hc12|-m68hcs12]
[-mshort|-mlong]
[-mshort-double|-mlong-double]
[--force-long-branchs] [--short-branchs]
[--strict-direct-mode] [--print-insn-syntax]
[--print-opcodes] [--generate-example]
Target MCORE options:
[-jsri2bsr] [-sifilter] [-relax]
[-mcpu=[210|340]]
Target MIPS options:
[-nocpp] [-EL] [-EB] [-O[optimization level]]
[-g[debug level]] [-G num] [-KPIC] [-call_shared]
[-non_shared] [-xgot]
[-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
[-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
[-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
[-mips64] [-mips64r2]
[-construct-floats] [-no-construct-floats]
[-trap] [-no-break] [-break] [-no-trap]
[-mfix7000] [-mno-fix7000]
[-mips16] [-no-mips16]
[-mips3d] [-no-mips3d]
[-mdmx] [-no-mdmx]
[-mdebug] [-no-mdebug]
[-mpdr] [-mno-pdr]
Target MMIX options:
[--fixed-special-register-names] [--globalize-symbols]
[--gnu-syntax] [--relax] [--no-predefined-symbols]
[--no-expand] [--no-merge-gregs] [-x]
[--linker-allocated-gregs]
Target PDP11 options:
[-mpic|-mno-pic] [-mall] [-mno-extensions]
[-mextension|-mno-extension]
[-mcpu] [-mmachine]
Target picoJava options:
[-mb|-me]
Target PowerPC options:
[-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|
-m403|-m405|-mppc64|-m620|-mppc64bridge|-mbooke|
-mbooke32|-mbooke64]
[-mcom|-many|-maltivec] [-memb]
[-mregnames|-mno-regnames]
[-mrelocatable|-mrelocatable-lib]
[-mlittle|-mlittle-endian|-mbig|-mbig-endian]
[-msolaris|-mno-solaris]
Target SPARC options:
[-Av6|-Av7|-Av8|-Asparclet|-Asparclite
-Av8plus|-Av8plusa|-Av9|-Av9a]
[-xarch=v8plus|-xarch=v8plusa] [-bump]
[-32|-64]
Target TIC54X options:
[-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
[-merrors-to-file <filename>|-me <filename>]
Target Xtensa options:
[--[no-]density] [--[no-]relax] [--[no-]generics]
[--[no-]text-section-literals]
[--[no-]target-align] [--[no-]longcalls] |
Turn on listings, in any of a variety of ways:
omit false conditionals
omit debugging directives
include high-level source
include assembly
include macro expansions
omit forms processing
include symbols
set the name of the listing file
You may combine these options; for example, use -aln for assembly listing without forms processing. The =file option, if used, must be the last one. By itself, -a defaults to -ahls.
Begin in alternate macro mode, see Section 8.61 .altmacro.
Ignored. This option is accepted for script compatibility with calls to other assemblers.
Define the symbol sym to be value before assembling the input file. value must be an integer constant. As in C, a leading 0x indicates a hexadecimal value, and a leading 0 indicates an octal value.
"fast"--skip whitespace and comment preprocessing (assume source is compiler output).
Generate debugging information for each assembler source line using whichever debug format is preferred by the target. This currently means either STABS, ECOFF or DWARF2.
Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it.
Generate stabs debugging information for each assembler line, with GNU extensions that probably only gdb can handle, and that could make other debuggers crash or refuse to read your program. This may help debugging assembler code. Currently the only GNU extension is the location of the current working directory at assembling time.
Generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note--this option is only supported by some targets, not all of them.
Print a summary of the command line options and exit.
Print a summary of all target specific options and exit.
Add directory dir to the search list for .include directives.
Don't warn about signed overflow.
Issue warnings when difference tables altered for long displacements.
Keep (in the symbol table) local symbols. On traditional a.out systems these start with L, but different systems have different local label prefixes.
Set the maximum width, in words, of the output data column for an assembler listing to number.
Set the maximum width, in words, of the output data column for continuation lines in an assembler listing to number.
Set the maximum width of an input source line, as displayed in a listing, to number bytes.
Set the maximum number of lines printed in a listing for a single line of input to number + 1.
Name the object-file output from as objfile.
Fold the data section into the text section.
Print the maximum space (in bytes) and total time (in seconds) used by assembly.
Remove local absolute symbols from the outgoing symbol table.
Print the as version.
Print the as version and exit.
Suppress warning messages.
Treat warnings as errors.
Don't suppress warning messages or treat them as errors.
Ignored.
Ignored.
Generate an object file even after errors.
Standard input, or source files to assemble.
The following options are available when as is configured for an ARC processor.
This option selects the core processor variant.
Select either big-endian (-EB) or little-endian (-EL) output.
The following options are available when as is configured for the ARM processor family.
Specify which ARM processor variant is the target.
Specify which ARM architecture variant is used by the target.
Select which Floating Point architecture is the target.
Select which floating point ABI is in use.
Enable Thumb only instruction decoding.
Select which procedure calling convention is in use.
Select either big-endian (-EB) or little-endian (-EL) output.
Specify that the code has been generated with interworking between Thumb and ARM code in mind.
Specify that PIC code has been generated.
See the info pages for documentation of the CRIS-specific options.
The following options are available when as is configured for a D10V processor.
Optimize output by parallelizing instructions.
The following options are available when as is configured for a D30V processor.
Optimize output by parallelizing instructions.
Warn when nops are generated.
Warn when a nop after a 32-bit multiply instruction is generated.
The following options are available when as is configured for the Intel 80960 processor.
Specify which variant of the 960 architecture is the target.
Add code to collect statistics about branches taken.
Do not alter compare-and-branch instructions for long displacements; error if necessary.
The following options are available when as is configured for the Ubicom IP2K series.
Specifies that the extended IP2022 instructions are allowed.
Restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones.
The following options are available when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series.
Specify which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to the M32RX.
Produce warning messages when questionable parallel constructs are encountered.
Do not produce warning messages when questionable parallel constructs are encountered.
The following options are available when as is configured for the Motorola 68000 series.
Shorten references to undefined symbols, to one word instead of two.
Specify what processor in the 68000 family is the target. The default is normally the 68020, but this can be changed at configuration time.
The target machine does (or does not) have a floating-point coprocessor. The default is to assume a coprocessor for 68020, 68030, and cpu32. Although the basic 68000 is not compatible with the 68881, a combination of the two can be specified, since it's possible to do emulation of the coprocessor instructions with the main processor.
The target machine does (or does not) have a memory-management unit coprocessor. The default is to assume an MMU for 68020 and up.
For details about the PDP-11 machine dependent features options, see Section 32.1 Options.
Generate position-independent (or position-dependent) code. The default is -mpic.
Enable all instruction set extensions. This is the default.
Disable all instruction set extensions.
Enable (or disable) a particular instruction set extension.
Enable the instruction set extensions supported by a particular CPU, and disable all other extensions.
Enable the instruction set extensions supported by a particular machine model, and disable all other extensions.
The following options are available when as is configured for a picoJava processor.
Generate "big endian" format output.
Generate "little endian" format output.
The following options are available when as is configured for the Motorola 68HC11 or 68HC12 series.
Specify what processor is the target. The default is defined by the configuration option when building the assembler.
Specify to use the 16-bit integer ABI.
Specify to use the 32-bit integer ABI.
Specify to use the 32-bit double ABI.
Specify to use the 64-bit double ABI.
Relative branches are turned into absolute ones. This concerns conditional branches, unconditional branches and branches to a sub routine.
Do not turn relative branchs into absolute ones when the offset is out of range.
Do not turn the direct addressing mode into extended addressing mode when the instruction does not support direct addressing mode.
Print the syntax of instruction in case of error.
print the list of instructions with syntax and then exit.
print an example of instruction for each possible instruction and then exit. This option is only useful for testing as.
The following options are available when as is configured for the SPARC architecture:
Explicitly select a variant of the SPARC architecture.
-Av8plus and -Av8plusa select a 32 bit environment. -Av9 and -Av9a select a 64 bit environment.
-Av8plusa and -Av9a enable the SPARC V9 instruction set with UltraSPARC extensions.
For compatibility with the Solaris v9 assembler. These options are equivalent to -Av8plus and -Av8plusa, respectively.
Warn when the assembler switches to another architecture.
The following options are available when as is configured for the 'c54x architecture.
Enable extended addressing mode. All addresses and relocations will assume extended addressing (usually 23 bits).
Sets the CPU version being compiled for.
Redirect error output to a file, for broken systems which don't support such behaviour in the shell.
The following options are available when as is configured for a mips processor.
This option sets the largest size of an object that can be referenced implicitly with the gp register. It is only accepted for targets that use ECOFF format, such as a DECstation running Ultrix. The default value is 8.
Generate "big endian" format output.
Generate "little endian" format output.
Generate code for a particular mips Instruction Set Architecture level. -mips1 is an alias for -march=r3000, -mips2 is an alias for -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an alias for -march=r8000. -mips5, -mips32, -mips32r2, -mips64, and -mips64r2 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS64, and MIPS64 Release 2 ISA processors, respectively.
Generate code for a particular mips cpu.
Schedule and tune for a particular mips cpu.
Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.
Cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard ELF .stabs sections.
Control generation of .pdr sections.
The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers.
Generate code for the MIPS 16 processor. This is equivalent to putting .set mips16 at the start of the assembly file. -no-mips16 turns off this option.
Generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions. -no-mips3d turns off this option.
Generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. -no-mdmx turns off this option.
The -no-construct-floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. By default -construct-floats is selected, allowing construction of these floating point constants.
This option causes as to emulate as configured for some other target, in all respects, including output format (choosing between ELF and ECOFF only), handling of pseudo-opcodes which may generate debugging information or store symbol table information, and default endianness. The available configuration names are: mipsecoff, mipself, mipslecoff, mipsbecoff, mipslelf, mipsbelf. The first two do not alter the default endianness from that of the primary target for which the assembler was configured; the others change the default to little- or big-endian as indicated by the b or l in the name. Using -EB or -EL will override the endianness selection in any case.
This option is currently supported only when the primary target as is configured for is a mips ELF or ECOFF target. Furthermore, the primary target or others specified with -enable-targets=… at configuration time must include support for the other format, if both are to be available. For example, the Irix 5 configuration includes support for both.
Eventually, this option will support more configurations, with more fine-grained control over the assembler's behavior, and will be supported for more processors.
as ignores this option. It is accepted for compatibility with the native tools.
Control how to deal with multiplication overflow and division by zero. -trap or -no-break (which are synonyms) take a trap exception (and only work for Instruction Set Architecture level 2 and higher); -break or -no-trap (also synonyms, and the default) take a break exception.
When this option is used, as will issue a warning every time it generates a nop instruction from a macro.
The following options are available when as is configured for an MCore processor.
Enable or disable the JSRI to BSR transformation. By default this is enabled. The command line option -nojsri2bsr can be used to disable it.
Enable or disable the silicon filter behaviour. By default this is disabled. The default can be overridden by the -sifilter command line option.
Alter jump instructions for long displacements.
Select the cpu type on the target hardware. This controls which instructions can be assembled.
Assemble for a big endian target.
Assemble for a little endian target.
See the info pages for documentation of the MMIX-specific options.
The following options are available when as is configured for an Xtensa processor.
Enable or disable use of instructions from the Xtensa code density option. This is enabled by default when the Xtensa processor supports the code density option.
Enable or disable instruction relaxation. This is enabled by default. Note: In the current implementation, these options also control whether assembler optimizations are performed, making these options equivalent to -generics and -no-generics.
Enable or disable all assembler transformations of Xtensa instructions. The default is -generics; -no-generics should be used only in the rare cases when the instructions must be exactly as specified in the assembly source.
With -text-section-literals, literal pools are interspersed in the text section. The default is -no-text-section-literals, which places literals in a separate section in the output file.
Enable or disable automatic alignment to reduce branch penalties at the expense of some code density. The default is -target-align.
Enable or disable transformation of call instructions to allow calls across a greater range of addresses. The default is -no-longcalls.
This manual is intended to describe what you need to know to use gnu as. We cover the syntax expected in source files, including notation for symbols, constants, and expressions; the directives that as understands; and of course how to invoke as.
This manual also describes some of the machine-dependent features of various flavors of the assembler.
On the other hand, this manual is not intended as an introduction to programming in assembly language--let alone programming in general! In a similar vein, we make no attempt to introduce the machine architecture; we do not describe the instruction set, standard mnemonics, registers or addressing modes that are standard to a particular architecture. You may want to consult the manufacturer's machine architecture manual for this information.