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| #define AX_LOOP 0x0C /* Loopback mode */ |
| #define AX_OFF 0x00 /* Irq off, buffer access on */ |
| #define AX_RX 0x48 /* Receive a packet */ |
| #define AX_STATUS (ioaddr + 0x0E) |
| #define AX_SYS 0x40 /* Load the buffer */ |
| #define AX_XMIT 0x44 /* Transmit a packet */ |
| #define DATAPORT (ioaddr + 0x0F) |
| #define EL1_DATAPORT 0x0f |
| #define EL_DEBUG 0 /* use 0 for production, 1 for devel., >2 for debug */ |
| #define GP_HIGH (ioaddr + 0x09) |
| #define GP_LOW (ioaddr + 0x08) |
| #define RX_BUF_CLR (ioaddr + 0x0A) |
| #define RX_GOOD 0x30 /* Good packet 0x20, or simple overflow 0x10. */ |
| #define RX_HIGH (ioaddr + 0x0B) |
| #define RX_LOW (ioaddr + 0x0A) |
| #define RX_MISSED 0x01 /* Missed a packet due to 3c501 braindamage. */ |
| #define RX_MULT 0xE8 /* Accept multicast packets. */ |
| #define RX_NORM 0xA8 /* 0x68 == all addrs, 0xA8 only to me. */ |
| #define RX_PROM 0x68 /* Senior Prom, uhmm promiscuous mode. */ |
| #define RX_STATUS (ioaddr + 0x06) |
| #define SAPROM (ioaddr + 0x0C) |
| #define TX_16COLLISIONS 0x04 |
| #define TX_COLLISION 0x02 |
| #define TX_NORM 0x0A /* Interrupt on everything that might hang the chip */ |
| #define TX_RDY 0x08 /* In TX_STATUS */ |
| #define TX_STATUS (ioaddr + 0x07) |