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57xx_hsi_bnx2fc.h
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1 #ifndef __57XX_FCOE_HSI_LINUX_LE__
2 #define __57XX_FCOE_HSI_LINUX_LE__
3 
4 /*
5  * common data for all protocols
6  */
7 struct b577xx_doorbell_hdr {
8  u8 header;
9 #define B577XX_DOORBELL_HDR_RX (0x1<<0)
10 #define B577XX_DOORBELL_HDR_RX_SHIFT 0
11 #define B577XX_DOORBELL_HDR_DB_TYPE (0x1<<1)
12 #define B577XX_DOORBELL_HDR_DB_TYPE_SHIFT 1
13 #define B577XX_DOORBELL_HDR_DPM_SIZE (0x3<<2)
14 #define B577XX_DOORBELL_HDR_DPM_SIZE_SHIFT 2
15 #define B577XX_DOORBELL_HDR_CONN_TYPE (0xF<<4)
16 #define B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT 4
17 };
18 
19 /*
20  * doorbell message sent to the chip
21  */
22 struct b577xx_doorbell {
23 #if defined(__BIG_ENDIAN)
24  u16 zero_fill2;
25  u8 zero_fill1;
26  struct b577xx_doorbell_hdr header;
27 #elif defined(__LITTLE_ENDIAN)
28  struct b577xx_doorbell_hdr header;
29  u8 zero_fill1;
30  u16 zero_fill2;
31 #endif
32 };
33 
34 
35 
36 /*
37  * doorbell message sent to the chip
38  */
39 struct b577xx_doorbell_set_prod {
40 #if defined(__BIG_ENDIAN)
41  u16 prod;
42  u8 zero_fill1;
43  struct b577xx_doorbell_hdr header;
44 #elif defined(__LITTLE_ENDIAN)
45  struct b577xx_doorbell_hdr header;
46  u8 zero_fill1;
47  u16 prod;
48 #endif
49 };
50 
51 
52 struct regpair {
53  __le32 lo;
54  __le32 hi;
55 };
56 
57 
58 /*
59  * ABTS info $$KEEP_ENDIANNESS$$
60  */
61 struct fcoe_abts_info {
62  __le16 aborted_task_id;
63  __le16 reserved0;
64  __le32 reserved1;
65 };
66 
67 
68 /*
69  * Fixed size structure in order to plant it in Union structure
70  * $$KEEP_ENDIANNESS$$
71  */
72 struct fcoe_abts_rsp_union {
73  u8 r_ctl;
74  u8 rsrv[3];
75  __le32 abts_rsp_payload[7];
76 };
77 
78 
79 /*
80  * 4 regs size $$KEEP_ENDIANNESS$$
81  */
82 struct fcoe_bd_ctx {
83  __le32 buf_addr_hi;
84  __le32 buf_addr_lo;
85  __le16 buf_len;
86  __le16 rsrv0;
87  __le16 flags;
88  __le16 rsrv1;
89 };
90 
91 
92 /*
93  * FCoE cached sges context $$KEEP_ENDIANNESS$$
94  */
95 struct fcoe_cached_sge_ctx {
96  struct regpair cur_buf_addr;
97  __le16 cur_buf_rem;
98  __le16 second_buf_rem;
99  struct regpair second_buf_addr;
100 };
101 
102 
103 /*
104  * Cleanup info $$KEEP_ENDIANNESS$$
105  */
106 struct fcoe_cleanup_info {
107  __le16 cleaned_task_id;
108  __le16 rolled_tx_seq_cnt;
109  __le32 rolled_tx_data_offset;
110 };
111 
112 
113 /*
114  * Fcp RSP flags $$KEEP_ENDIANNESS$$
115  */
116 struct fcoe_fcp_rsp_flags {
117  u8 flags;
118 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0)
119 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0
120 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1)
121 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1
122 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2)
123 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2
124 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3)
125 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3
126 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4)
127 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4
128 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5)
129 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5
130 };
131 
132 /*
133  * Fcp RSP payload $$KEEP_ENDIANNESS$$
134  */
135 struct fcoe_fcp_rsp_payload {
136  struct regpair reserved0;
137  __le32 fcp_resid;
138  u8 scsi_status_code;
139  struct fcoe_fcp_rsp_flags fcp_flags;
140  __le16 retry_delay_timer;
141  __le32 fcp_rsp_len;
142  __le32 fcp_sns_len;
143 };
144 
145 /*
146  * Fixed size structure in order to plant it in Union structure
147  * $$KEEP_ENDIANNESS$$
148  */
149 struct fcoe_fcp_rsp_union {
150  struct fcoe_fcp_rsp_payload payload;
151  struct regpair reserved0;
152 };
153 
154 /*
155  * FC header $$KEEP_ENDIANNESS$$
156  */
157 struct fcoe_fc_hdr {
158  u8 s_id[3];
159  u8 cs_ctl;
160  u8 d_id[3];
161  u8 r_ctl;
162  __le16 seq_cnt;
163  u8 df_ctl;
164  u8 seq_id;
165  u8 f_ctl[3];
166  u8 type;
167  __le32 parameters;
168  __le16 rx_id;
169  __le16 ox_id;
170 };
171 
172 /*
173  * FC header union $$KEEP_ENDIANNESS$$
174  */
175 struct fcoe_mp_rsp_union {
176  struct fcoe_fc_hdr fc_hdr;
177  __le32 mp_payload_len;
178  __le32 rsrv;
179 };
180 
181 /*
182  * Completion information $$KEEP_ENDIANNESS$$
183  */
184 union fcoe_comp_flow_info {
185  struct fcoe_fcp_rsp_union fcp_rsp;
186  struct fcoe_abts_rsp_union abts_rsp;
187  struct fcoe_mp_rsp_union mp_rsp;
188  __le32 opaque[8];
189 };
190 
191 
192 /*
193  * External ABTS info $$KEEP_ENDIANNESS$$
194  */
195 struct fcoe_ext_abts_info {
196  __le32 rsrv0[6];
197  struct fcoe_abts_info ctx;
198 };
199 
200 
201 /*
202  * External cleanup info $$KEEP_ENDIANNESS$$
203  */
204 struct fcoe_ext_cleanup_info {
205  __le32 rsrv0[6];
206  struct fcoe_cleanup_info ctx;
207 };
208 
209 
210 /*
211  * Fcoe FW Tx sequence context $$KEEP_ENDIANNESS$$
212  */
213 struct fcoe_fw_tx_seq_ctx {
214  __le32 data_offset;
215  __le16 seq_cnt;
216  __le16 rsrv0;
217 };
218 
219 /*
220  * Fcoe external FW Tx sequence context $$KEEP_ENDIANNESS$$
221  */
222 struct fcoe_ext_fw_tx_seq_ctx {
223  __le32 rsrv0[6];
224  struct fcoe_fw_tx_seq_ctx ctx;
225 };
226 
227 
228 /*
229  * FCoE multiple sges context $$KEEP_ENDIANNESS$$
230  */
231 struct fcoe_mul_sges_ctx {
232  struct regpair cur_sge_addr;
233  __le16 cur_sge_off;
234  u8 cur_sge_idx;
235  u8 sgl_size;
236 };
237 
238 /*
239  * FCoE external multiple sges context $$KEEP_ENDIANNESS$$
240  */
241 struct fcoe_ext_mul_sges_ctx {
242  struct fcoe_mul_sges_ctx mul_sgl;
243  struct regpair rsrv0;
244 };
245 
246 
247 /*
248  * FCP CMD payload $$KEEP_ENDIANNESS$$
249  */
250 struct fcoe_fcp_cmd_payload {
251  __le32 opaque[8];
252 };
253 
254 
255 
256 
257 
258 /*
259  * Fcp xfr rdy payload $$KEEP_ENDIANNESS$$
260  */
261 struct fcoe_fcp_xfr_rdy_payload {
262  __le32 burst_len;
263  __le32 data_ro;
264 };
265 
266 
267 /*
268  * FC frame $$KEEP_ENDIANNESS$$
269  */
270 struct fcoe_fc_frame {
271  struct fcoe_fc_hdr fc_hdr;
272  __le32 reserved0[2];
273 };
274 
275 
276 
277 
278 /*
279  * FCoE KCQ CQE parameters $$KEEP_ENDIANNESS$$
280  */
281 union fcoe_kcqe_params {
282  __le32 reserved0[4];
283 };
284 
285 /*
286  * FCoE KCQ CQE $$KEEP_ENDIANNESS$$
287  */
288 struct fcoe_kcqe {
289  __le32 fcoe_conn_id;
290  __le32 completion_status;
291  __le32 fcoe_conn_context_id;
292  union fcoe_kcqe_params params;
293  __le16 qe_self_seq;
294  u8 op_code;
295  u8 flags;
296 #define FCOE_KCQE_RESERVED0 (0x7<<0)
297 #define FCOE_KCQE_RESERVED0_SHIFT 0
298 #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
299 #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
300 #define FCOE_KCQE_LAYER_CODE (0x7<<4)
301 #define FCOE_KCQE_LAYER_CODE_SHIFT 4
302 #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
303 #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
304 };
305 
306 
307 
308 /*
309  * FCoE KWQE header $$KEEP_ENDIANNESS$$
310  */
311 struct fcoe_kwqe_header {
312  u8 op_code;
313  u8 flags;
314 #define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
315 #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
316 #define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
317 #define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
318 #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
319 #define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
320 };
321 
322 /*
323  * FCoE firmware init request 1 $$KEEP_ENDIANNESS$$
324  */
325 struct fcoe_kwqe_init1 {
326  __le16 num_tasks;
327  struct fcoe_kwqe_header hdr;
328  __le32 task_list_pbl_addr_lo;
329  __le32 task_list_pbl_addr_hi;
330  __le32 dummy_buffer_addr_lo;
331  __le32 dummy_buffer_addr_hi;
332  __le16 sq_num_wqes;
333  __le16 rq_num_wqes;
334  __le16 rq_buffer_log_size;
335  __le16 cq_num_wqes;
336  __le16 mtu;
337  u8 num_sessions_log;
338  u8 flags;
339 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
340 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
341 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
342 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
343 #define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
344 #define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
345 };
346 
347 /*
348  * FCoE firmware init request 2 $$KEEP_ENDIANNESS$$
349  */
350 struct fcoe_kwqe_init2 {
351  u8 hsi_major_version;
352  u8 hsi_minor_version;
353  struct fcoe_kwqe_header hdr;
354  __le32 hash_tbl_pbl_addr_lo;
355  __le32 hash_tbl_pbl_addr_hi;
356  __le32 t2_hash_tbl_addr_lo;
357  __le32 t2_hash_tbl_addr_hi;
358  __le32 t2_ptr_hash_tbl_addr_lo;
359  __le32 t2_ptr_hash_tbl_addr_hi;
360  __le32 free_list_count;
361 };
362 
363 /*
364  * FCoE firmware init request 3 $$KEEP_ENDIANNESS$$
365  */
366 struct fcoe_kwqe_init3 {
367  __le16 reserved0;
368  struct fcoe_kwqe_header hdr;
369  __le32 error_bit_map_lo;
370  __le32 error_bit_map_hi;
371  u8 perf_config;
372  u8 reserved21[3];
373  __le32 reserved2[4];
374 };
375 
376 /*
377  * FCoE connection offload request 1 $$KEEP_ENDIANNESS$$
378  */
379 struct fcoe_kwqe_conn_offload1 {
380  __le16 fcoe_conn_id;
381  struct fcoe_kwqe_header hdr;
382  __le32 sq_addr_lo;
383  __le32 sq_addr_hi;
384  __le32 rq_pbl_addr_lo;
385  __le32 rq_pbl_addr_hi;
386  __le32 rq_first_pbe_addr_lo;
387  __le32 rq_first_pbe_addr_hi;
388  __le16 rq_prod;
389  __le16 reserved0;
390 };
391 
392 /*
393  * FCoE connection offload request 2 $$KEEP_ENDIANNESS$$
394  */
395 struct fcoe_kwqe_conn_offload2 {
396  __le16 tx_max_fc_pay_len;
397  struct fcoe_kwqe_header hdr;
398  __le32 cq_addr_lo;
399  __le32 cq_addr_hi;
400  __le32 xferq_addr_lo;
401  __le32 xferq_addr_hi;
402  __le32 conn_db_addr_lo;
403  __le32 conn_db_addr_hi;
404  __le32 reserved1;
405 };
406 
407 /*
408  * FCoE connection offload request 3 $$KEEP_ENDIANNESS$$
409  */
410 struct fcoe_kwqe_conn_offload3 {
411  __le16 vlan_tag;
412 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
413 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
414 #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
415 #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
416 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
417 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
418  struct fcoe_kwqe_header hdr;
419  u8 s_id[3];
420  u8 tx_max_conc_seqs_c3;
421  u8 d_id[3];
422  u8 flags;
423 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
424 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
425 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
426 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
427 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
428 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
429 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
430 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
431 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
432 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
433 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
434 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
435 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
436 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
437 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
438 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
439  __le32 reserved;
440  __le32 confq_first_pbe_addr_lo;
441  __le32 confq_first_pbe_addr_hi;
442  __le16 tx_total_conc_seqs;
443  __le16 rx_max_fc_pay_len;
444  __le16 rx_total_conc_seqs;
445  u8 rx_max_conc_seqs_c3;
446  u8 rx_open_seqs_exch_c3;
447 };
448 
449 /*
450  * FCoE connection offload request 4 $$KEEP_ENDIANNESS$$
451  */
452 struct fcoe_kwqe_conn_offload4 {
453  u8 e_d_tov_timer_val;
454  u8 reserved2;
455  struct fcoe_kwqe_header hdr;
456  u8 src_mac_addr_lo[2];
457  u8 src_mac_addr_mid[2];
458  u8 src_mac_addr_hi[2];
459  u8 dst_mac_addr_hi[2];
460  u8 dst_mac_addr_lo[2];
461  u8 dst_mac_addr_mid[2];
462  __le32 lcq_addr_lo;
463  __le32 lcq_addr_hi;
464  __le32 confq_pbl_base_addr_lo;
465  __le32 confq_pbl_base_addr_hi;
466 };
467 
468 /*
469  * FCoE connection enable request $$KEEP_ENDIANNESS$$
470  */
471 struct fcoe_kwqe_conn_enable_disable {
472  __le16 reserved0;
473  struct fcoe_kwqe_header hdr;
474  u8 src_mac_addr_lo[2];
475  u8 src_mac_addr_mid[2];
476  u8 src_mac_addr_hi[2];
477  u16 vlan_tag;
478 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
479 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
480 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
481 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
482 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
483 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
484  u8 dst_mac_addr_lo[2];
485  u8 dst_mac_addr_mid[2];
486  u8 dst_mac_addr_hi[2];
487  __le16 reserved1;
488  u8 s_id[3];
489  u8 vlan_flag;
490  u8 d_id[3];
491  u8 reserved3;
492  __le32 context_id;
493  __le32 conn_id;
494  __le32 reserved4;
495 };
496 
497 /*
498  * FCoE connection destroy request $$KEEP_ENDIANNESS$$
499  */
500 struct fcoe_kwqe_conn_destroy {
501  __le16 reserved0;
502  struct fcoe_kwqe_header hdr;
503  __le32 context_id;
504  __le32 conn_id;
505  __le32 reserved1[5];
506 };
507 
508 /*
509  * FCoe destroy request $$KEEP_ENDIANNESS$$
510  */
511 struct fcoe_kwqe_destroy {
512  __le16 reserved0;
513  struct fcoe_kwqe_header hdr;
514  __le32 reserved1[7];
515 };
516 
517 /*
518  * FCoe statistics request $$KEEP_ENDIANNESS$$
519  */
520 struct fcoe_kwqe_stat {
521  __le16 reserved0;
522  struct fcoe_kwqe_header hdr;
523  __le32 stat_params_addr_lo;
524  __le32 stat_params_addr_hi;
525  __le32 reserved1[5];
526 };
527 
528 /*
529  * FCoE KWQ WQE $$KEEP_ENDIANNESS$$
530  */
531 union fcoe_kwqe {
532  struct fcoe_kwqe_init1 init1;
533  struct fcoe_kwqe_init2 init2;
534  struct fcoe_kwqe_init3 init3;
535  struct fcoe_kwqe_conn_offload1 conn_offload1;
536  struct fcoe_kwqe_conn_offload2 conn_offload2;
537  struct fcoe_kwqe_conn_offload3 conn_offload3;
538  struct fcoe_kwqe_conn_offload4 conn_offload4;
539  struct fcoe_kwqe_conn_enable_disable conn_enable_disable;
540  struct fcoe_kwqe_conn_destroy conn_destroy;
541  struct fcoe_kwqe_destroy destroy;
542  struct fcoe_kwqe_stat statistics;
543 };
544 
545 
546 
547 
548 
549 
550 
551 
552 
553 
554 
555 
556 
557 
558 
559 
560 /*
561  * TX SGL context $$KEEP_ENDIANNESS$$
562  */
563 union fcoe_sgl_union_ctx {
564  struct fcoe_cached_sge_ctx cached_sge;
565  struct fcoe_ext_mul_sges_ctx sgl;
566  __le32 opaque[5];
567 };
568 
569 /*
570  * Data-In/ELS/BLS information $$KEEP_ENDIANNESS$$
571  */
572 struct fcoe_read_flow_info {
573  union fcoe_sgl_union_ctx sgl_ctx;
574  __le32 rsrv0[3];
575 };
576 
577 
578 /*
579  * Fcoe stat context $$KEEP_ENDIANNESS$$
580  */
581 struct fcoe_s_stat_ctx {
582  u8 flags;
583 #define FCOE_S_STAT_CTX_ACTIVE (0x1<<0)
584 #define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0
585 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1)
586 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1
587 #define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2)
588 #define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2
589 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3)
590 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3
591 #define FCOE_S_STAT_CTX_P_RJT (0x1<<4)
592 #define FCOE_S_STAT_CTX_P_RJT_SHIFT 4
593 #define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5)
594 #define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5
595 #define FCOE_S_STAT_CTX_RSRV1 (0x3<<6)
596 #define FCOE_S_STAT_CTX_RSRV1_SHIFT 6
597 };
598 
599 /*
600  * Fcoe rx seq context $$KEEP_ENDIANNESS$$
601  */
602 struct fcoe_rx_seq_ctx {
603  u8 seq_id;
604  struct fcoe_s_stat_ctx s_stat;
605  __le16 seq_cnt;
606  __le32 low_exp_ro;
607  __le32 high_exp_ro;
608 };
609 
610 
611 /*
612  * Fcoe rx_wr union context $$KEEP_ENDIANNESS$$
613  */
614 union fcoe_rx_wr_union_ctx {
615  struct fcoe_read_flow_info read_info;
616  union fcoe_comp_flow_info comp_info;
617  __le32 opaque[8];
618 };
619 
620 
621 
622 /*
623  * FCoE SQ element $$KEEP_ENDIANNESS$$
624  */
625 struct fcoe_sqe {
626  __le16 wqe;
627 #define FCOE_SQE_TASK_ID (0x7FFF<<0)
628 #define FCOE_SQE_TASK_ID_SHIFT 0
629 #define FCOE_SQE_TOGGLE_BIT (0x1<<15)
630 #define FCOE_SQE_TOGGLE_BIT_SHIFT 15
631 };
632 
633 
634 
635 /*
636  * 14 regs $$KEEP_ENDIANNESS$$
637  */
638 struct fcoe_tce_tx_only {
639  union fcoe_sgl_union_ctx sgl_ctx;
640  __le32 rsrv0;
641 };
642 
643 /*
644  * 32 bytes (8 regs) used for TX only purposes $$KEEP_ENDIANNESS$$
645  */
646 union fcoe_tx_wr_rx_rd_union_ctx {
647  struct fcoe_fc_frame tx_frame;
648  struct fcoe_fcp_cmd_payload fcp_cmd;
649  struct fcoe_ext_cleanup_info cleanup;
650  struct fcoe_ext_abts_info abts;
651  struct fcoe_ext_fw_tx_seq_ctx tx_seq;
652  __le32 opaque[8];
653 };
654 
655 /*
656  * tce_tx_wr_rx_rd_const $$KEEP_ENDIANNESS$$
657  */
658 struct fcoe_tce_tx_wr_rx_rd_const {
659  u8 init_flags;
660 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE (0x7<<0)
661 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT 0
662 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE (0x1<<3)
663 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT 3
664 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE (0x1<<4)
665 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT 4
666 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE (0x3<<5)
667 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT 5
668 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV (0x1<<7)
669 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV_SHIFT 7
670  u8 tx_flags;
671 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID (0x1<<0)
672 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID_SHIFT 0
673 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE (0xF<<1)
674 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT 1
675 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1 (0x1<<5)
676 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1_SHIFT 5
677 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6)
678 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT_SHIFT 6
679 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2 (0x1<<7)
680 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2_SHIFT 7
681  __le16 rsrv3;
682  __le32 verify_tx_seq;
683 };
684 
685 /*
686  * tce_tx_wr_rx_rd $$KEEP_ENDIANNESS$$
687  */
688 struct fcoe_tce_tx_wr_rx_rd {
689  union fcoe_tx_wr_rx_rd_union_ctx union_ctx;
690  struct fcoe_tce_tx_wr_rx_rd_const const_ctx;
691 };
692 
693 /*
694  * tce_rx_wr_tx_rd_const $$KEEP_ENDIANNESS$$
695  */
696 struct fcoe_tce_rx_wr_tx_rd_const {
697  __le32 data_2_trns;
698  __le32 init_flags;
699 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID (0xFFFFFF<<0)
700 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT 0
701 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0 (0xFF<<24)
702 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0_SHIFT 24
703 };
704 
705 /*
706  * tce_rx_wr_tx_rd_var $$KEEP_ENDIANNESS$$
707  */
708 struct fcoe_tce_rx_wr_tx_rd_var {
709  __le16 rx_flags;
710 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1 (0xF<<0)
711 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1_SHIFT 0
712 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE (0x7<<4)
713 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT 4
714 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ (0x1<<7)
715 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ_SHIFT 7
716 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE (0xF<<8)
717 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT 8
718 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME (0x1<<12)
719 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT 12
720 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT (0x1<<13)
721 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT_SHIFT 13
722 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2 (0x1<<14)
723 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2_SHIFT 14
724 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID (0x1<<15)
725 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID_SHIFT 15
726  __le16 rx_id;
727  struct fcoe_fcp_xfr_rdy_payload fcp_xfr_rdy;
728 };
729 
730 /*
731  * tce_rx_wr_tx_rd $$KEEP_ENDIANNESS$$
732  */
733 struct fcoe_tce_rx_wr_tx_rd {
734  struct fcoe_tce_rx_wr_tx_rd_const const_ctx;
735  struct fcoe_tce_rx_wr_tx_rd_var var_ctx;
736 };
737 
738 /*
739  * tce_rx_only $$KEEP_ENDIANNESS$$
740  */
741 struct fcoe_tce_rx_only {
742  struct fcoe_rx_seq_ctx rx_seq_ctx;
743  union fcoe_rx_wr_union_ctx union_ctx;
744 };
745 
746 /*
747  * task_ctx_entry $$KEEP_ENDIANNESS$$
748  */
749 struct fcoe_task_ctx_entry {
750  struct fcoe_tce_tx_only txwr_only;
751  struct fcoe_tce_tx_wr_rx_rd txwr_rxrd;
752  struct fcoe_tce_rx_wr_tx_rd rxwr_txrd;
753  struct fcoe_tce_rx_only rxwr_only;
754 };
755 
756 
757 
758 
759 
760 
761 
762 
763 
764 
765 /*
766  * FCoE XFRQ element $$KEEP_ENDIANNESS$$
767  */
768 struct fcoe_xfrqe {
769  __le16 wqe;
770 #define FCOE_XFRQE_TASK_ID (0x7FFF<<0)
771 #define FCOE_XFRQE_TASK_ID_SHIFT 0
772 #define FCOE_XFRQE_TOGGLE_BIT (0x1<<15)
773 #define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15
774 };
775 
776 
777 /*
778  * fcoe rx doorbell message sent to the chip $$KEEP_ENDIANNESS$$
779  */
780 struct b577xx_fcoe_rx_doorbell {
781  struct b577xx_doorbell_hdr hdr;
782  u8 params;
783 #define B577XX_FCOE_RX_DOORBELL_NEGATIVE_ARM (0x1F<<0)
784 #define B577XX_FCOE_RX_DOORBELL_NEGATIVE_ARM_SHIFT 0
785 #define B577XX_FCOE_RX_DOORBELL_OPCODE (0x7<<5)
786 #define B577XX_FCOE_RX_DOORBELL_OPCODE_SHIFT 5
787  __le16 doorbell_cq_cons;
788 };
789 
790 
791 /*
792  * FCoE CONFQ element $$KEEP_ENDIANNESS$$
793  */
794 struct fcoe_confqe {
795  __le16 ox_id;
796  __le16 rx_id;
797  __le32 param;
798 };
799 
800 
801 /*
802  * FCoE conection data base
803  */
804 struct fcoe_conn_db {
805 #if defined(__BIG_ENDIAN)
806  u16 rsrv0;
807  u16 rq_prod;
808 #elif defined(__LITTLE_ENDIAN)
809  u16 rq_prod;
810  u16 rsrv0;
811 #endif
812  u32 rsrv1;
813  struct regpair cq_arm;
814 };
815 
816 
817 /*
818  * FCoE CQ element $$KEEP_ENDIANNESS$$
819  */
820 struct fcoe_cqe {
821  __le16 wqe;
822 #define FCOE_CQE_CQE_INFO (0x3FFF<<0)
823 #define FCOE_CQE_CQE_INFO_SHIFT 0
824 #define FCOE_CQE_CQE_TYPE (0x1<<14)
825 #define FCOE_CQE_CQE_TYPE_SHIFT 14
826 #define FCOE_CQE_TOGGLE_BIT (0x1<<15)
827 #define FCOE_CQE_TOGGLE_BIT_SHIFT 15
828 };
829 
830 
831 /*
832  * FCoE error/warning reporting entry $$KEEP_ENDIANNESS$$
833  */
834 struct fcoe_partial_err_report_entry {
835  __le32 err_warn_bitmap_lo;
836  __le32 err_warn_bitmap_hi;
837  __le32 tx_buf_off;
838  __le32 rx_buf_off;
839 };
840 
841 /*
842  * FCoE error/warning reporting entry $$KEEP_ENDIANNESS$$
843  */
844 struct fcoe_err_report_entry {
845  struct fcoe_partial_err_report_entry data;
846  struct fcoe_fc_hdr fc_hdr;
847 };
848 
849 
850 /*
851  * FCoE hash table entry (32 bytes) $$KEEP_ENDIANNESS$$
852  */
853 struct fcoe_hash_table_entry {
854  u8 s_id_0;
855  u8 s_id_1;
856  u8 s_id_2;
857  u8 d_id_0;
858  u8 d_id_1;
859  u8 d_id_2;
860  __le16 dst_mac_addr_hi;
861  __le16 dst_mac_addr_mid;
862  __le16 dst_mac_addr_lo;
863  __le16 src_mac_addr_hi;
864  __le16 vlan_id;
865  __le16 src_mac_addr_lo;
866  __le16 src_mac_addr_mid;
867  u8 vlan_flag;
868  u8 reserved0;
869  __le16 reserved1;
870  __le32 reserved2;
871  __le32 field_id;
872 #define FCOE_HASH_TABLE_ENTRY_CID (0xFFFFFF<<0)
873 #define FCOE_HASH_TABLE_ENTRY_CID_SHIFT 0
874 #define FCOE_HASH_TABLE_ENTRY_RESERVED3 (0x7F<<24)
875 #define FCOE_HASH_TABLE_ENTRY_RESERVED3_SHIFT 24
876 #define FCOE_HASH_TABLE_ENTRY_VALID (0x1<<31)
877 #define FCOE_HASH_TABLE_ENTRY_VALID_SHIFT 31
878 };
879 
880 
881 /*
882  * FCoE LCQ element $$KEEP_ENDIANNESS$$
883  */
884 struct fcoe_lcqe {
885  __le32 wqe;
886 #define FCOE_LCQE_TASK_ID (0xFFFF<<0)
887 #define FCOE_LCQE_TASK_ID_SHIFT 0
888 #define FCOE_LCQE_LCQE_TYPE (0xFF<<16)
889 #define FCOE_LCQE_LCQE_TYPE_SHIFT 16
890 #define FCOE_LCQE_RESERVED (0xFF<<24)
891 #define FCOE_LCQE_RESERVED_SHIFT 24
892 };
893 
894 
895 
896 /*
897  * FCoE pending work request CQE $$KEEP_ENDIANNESS$$
898  */
899 struct fcoe_pend_wq_cqe {
900  __le16 wqe;
901 #define FCOE_PEND_WQ_CQE_TASK_ID (0x3FFF<<0)
902 #define FCOE_PEND_WQ_CQE_TASK_ID_SHIFT 0
903 #define FCOE_PEND_WQ_CQE_CQE_TYPE (0x1<<14)
904 #define FCOE_PEND_WQ_CQE_CQE_TYPE_SHIFT 14
905 #define FCOE_PEND_WQ_CQE_TOGGLE_BIT (0x1<<15)
906 #define FCOE_PEND_WQ_CQE_TOGGLE_BIT_SHIFT 15
907 };
908 
909 
910 /*
911  * FCoE RX statistics parameters section#0 $$KEEP_ENDIANNESS$$
912  */
913 struct fcoe_rx_stat_params_section0 {
914  __le32 fcoe_rx_pkt_cnt;
915  __le32 fcoe_rx_byte_cnt;
916 };
917 
918 
919 /*
920  * FCoE RX statistics parameters section#1 $$KEEP_ENDIANNESS$$
921  */
922 struct fcoe_rx_stat_params_section1 {
923  __le32 fcoe_ver_cnt;
924  __le32 fcoe_rx_drop_pkt_cnt;
925 };
926 
927 
928 /*
929  * FCoE RX statistics parameters section#2 $$KEEP_ENDIANNESS$$
930  */
931 struct fcoe_rx_stat_params_section2 {
932  __le32 fc_crc_cnt;
933  __le32 eofa_del_cnt;
934  __le32 miss_frame_cnt;
935  __le32 seq_timeout_cnt;
936  __le32 drop_seq_cnt;
937  __le32 fcoe_rx_drop_pkt_cnt;
938  __le32 fcp_rx_pkt_cnt;
939  __le32 reserved0;
940 };
941 
942 
943 /*
944  * FCoE TX statistics parameters $$KEEP_ENDIANNESS$$
945  */
946 struct fcoe_tx_stat_params {
947  __le32 fcoe_tx_pkt_cnt;
948  __le32 fcoe_tx_byte_cnt;
949  __le32 fcp_tx_pkt_cnt;
950  __le32 reserved0;
951 };
952 
953 /*
954  * FCoE statistics parameters $$KEEP_ENDIANNESS$$
955  */
956 struct fcoe_statistics_params {
957  struct fcoe_tx_stat_params tx_stat;
958  struct fcoe_rx_stat_params_section0 rx_stat0;
959  struct fcoe_rx_stat_params_section1 rx_stat1;
960  struct fcoe_rx_stat_params_section2 rx_stat2;
961 };
962 
963 
964 /*
965  * FCoE t2 hash table entry (64 bytes) $$KEEP_ENDIANNESS$$
966  */
967 struct fcoe_t2_hash_table_entry {
968  struct fcoe_hash_table_entry data;
969  struct regpair next;
970  struct regpair reserved0[3];
971 };
972 
973 
974 
975 /*
976  * FCoE unsolicited CQE $$KEEP_ENDIANNESS$$
977  */
978 struct fcoe_unsolicited_cqe {
979  __le16 wqe;
980 #define FCOE_UNSOLICITED_CQE_SUBTYPE (0x3<<0)
981 #define FCOE_UNSOLICITED_CQE_SUBTYPE_SHIFT 0
982 #define FCOE_UNSOLICITED_CQE_PKT_LEN (0xFFF<<2)
983 #define FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT 2
984 #define FCOE_UNSOLICITED_CQE_CQE_TYPE (0x1<<14)
985 #define FCOE_UNSOLICITED_CQE_CQE_TYPE_SHIFT 14
986 #define FCOE_UNSOLICITED_CQE_TOGGLE_BIT (0x1<<15)
987 #define FCOE_UNSOLICITED_CQE_TOGGLE_BIT_SHIFT 15
988 };
989 
990 #endif /* __57XX_FCOE_HSI_LINUX_LE__ */
Generated on Thu Jan 10 2013 14:19:54 for Linux Kernel by   doxygen 1.8.2