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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Go to the source code of this file.
| #define EASIL1_MMUMMU_CAM_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 226) |
Definition at line 42 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_CNTLMMU_ENABLE_WRITE32 (MMU_BASE_EASIL1 + 190) |
Definition at line 31 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_CNTLTWL_ENABLE_READ32 (MMU_BASE_EASIL1 + 174) |
Definition at line 29 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_CNTLTWL_ENABLE_WRITE32 (MMU_BASE_EASIL1 + 180) |
Definition at line 30 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_FAULT_AD_READ_REGISTER32 (MMU_BASE_EASIL1 + 194) |
Definition at line 32 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 322) |
Definition at line 44 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_IRQENABLE_READ_REGISTER32 (MMU_BASE_EASIL1 + 102) |
Definition at line 26 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_IRQENABLE_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 103) |
Definition at line 27 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_IRQSTATUS_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 51) |
Definition at line 25 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_LD_TLB_READ_REGISTER32 (MMU_BASE_EASIL1 + 213) |
Definition at line 40 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_LD_TLB_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 214) |
Definition at line 41 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_LOCK_BASE_VALUE_READ32 (MMU_BASE_EASIL1 + 205) |
Definition at line 36 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_READ32 (MMU_BASE_EASIL1 + 209) |
Definition at line 37 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_SET32 (MMU_BASE_EASIL1 + 212) |
Definition at line 39 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_WRITE32 (MMU_BASE_EASIL1 + 211) |
Definition at line 38 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_LOCK_READ_REGISTER32 (MMU_BASE_EASIL1 + 203) |
Definition at line 34 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_LOCK_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 204) |
Definition at line 35 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_RAM_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 268) |
Definition at line 43 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32 (MMU_BASE_EASIL1 + 39) |
Definition at line 24 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32 (MMU_BASE_EASIL1 + 17) |
Definition at line 23 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_SYSCONFIG_READ_REGISTER32 (MMU_BASE_EASIL1 + 3) |
Definition at line 22 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_TTB_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 198) |
Definition at line 33 of file MMUAccInt.h.
| #define EASIL1_MMUMMU_WALKING_STTWL_RUNNING_READ32 (MMU_BASE_EASIL1 + 156) |
Definition at line 28 of file MMUAccInt.h.
| #define MMU_MMU_CAM_OFFSET 0x58 |
Definition at line 56 of file MMUAccInt.h.
| #define MMU_MMU_CNTL_MMU_ENABLE_MASK 0x2 |
Definition at line 69 of file MMUAccInt.h.
| #define MMU_MMU_CNTL_MMU_ENABLE_OFFSET 1 |
Definition at line 70 of file MMUAccInt.h.
| #define MMU_MMU_CNTL_OFFSET 0x44 |
Definition at line 51 of file MMUAccInt.h.
| #define MMU_MMU_CNTL_TWL_ENABLE_MASK 0x4 |
Definition at line 67 of file MMUAccInt.h.
| #define MMU_MMU_CNTL_TWL_ENABLE_OFFSET 2 |
Definition at line 68 of file MMUAccInt.h.
| #define MMU_MMU_FAULT_AD_OFFSET 0x48 |
Definition at line 52 of file MMUAccInt.h.
| #define MMU_MMU_FLUSH_ENTRY_OFFSET 0x64 |
Definition at line 59 of file MMUAccInt.h.
| #define MMU_MMU_GFLUSH_OFFSET 0x60 |
Definition at line 58 of file MMUAccInt.h.
| #define MMU_MMU_IRQENABLE_OFFSET 0x1c |
Definition at line 49 of file MMUAccInt.h.
| #define MMU_MMU_IRQSTATUS_OFFSET 0x18 |
Definition at line 48 of file MMUAccInt.h.
| #define MMU_MMU_LD_TLB_OFFSET 0x54 |
Definition at line 55 of file MMUAccInt.h.
| #define MMU_MMU_LOCK_BASE_VALUE_MASK 0xfc00 |
Definition at line 71 of file MMUAccInt.h.
| #define MMU_MMU_LOCK_BASE_VALUE_OFFSET 10 |
Definition at line 72 of file MMUAccInt.h.
| #define MMU_MMU_LOCK_CURRENT_VICTIM_MASK 0x3f0 |
Definition at line 73 of file MMUAccInt.h.
| #define MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET 4 |
Definition at line 74 of file MMUAccInt.h.
| #define MMU_MMU_LOCK_OFFSET 0x50 |
Definition at line 54 of file MMUAccInt.h.
| #define MMU_MMU_RAM_OFFSET 0x5c |
Definition at line 57 of file MMUAccInt.h.
| #define MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK 0x1 |
Definition at line 63 of file MMUAccInt.h.
| #define MMU_MMU_SYSCONFIG_AUTO_IDLE_OFFSET 0 |
Definition at line 64 of file MMUAccInt.h.
| #define MMU_MMU_SYSCONFIG_IDLE_MODE_MASK 0x18 |
Definition at line 61 of file MMUAccInt.h.
| #define MMU_MMU_SYSCONFIG_IDLE_MODE_OFFSET 3 |
Definition at line 62 of file MMUAccInt.h.
| #define MMU_MMU_SYSCONFIG_OFFSET 0x10 |
Definition at line 47 of file MMUAccInt.h.
| #define MMU_MMU_TTB_OFFSET 0x4c |
Definition at line 53 of file MMUAccInt.h.
| #define MMU_MMU_WALKING_ST_OFFSET 0x40 |
Definition at line 50 of file MMUAccInt.h.
| #define MMU_MMU_WALKING_ST_TWL_RUNNING_MASK 0x1 |
Definition at line 65 of file MMUAccInt.h.
| #define MMU_MMU_WALKING_ST_TWL_RUNNING_OFFSET 0 |
Definition at line 66 of file MMUAccInt.h.
1.8.2