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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Data Structures | |
| struct | NCR5380_hostdata |
Macros | |
| #define | NCR5380_PUBLIC_RELEASE 7 |
| #define | NCR53C400_PUBLIC_RELEASE 2 |
| #define | NDEBUG_ARBITRATION 0x1 |
| #define | NDEBUG_AUTOSENSE 0x2 |
| #define | NDEBUG_DMA 0x4 |
| #define | NDEBUG_HANDSHAKE 0x8 |
| #define | NDEBUG_INFORMATION 0x10 |
| #define | NDEBUG_INIT 0x20 |
| #define | NDEBUG_INTR 0x40 |
| #define | NDEBUG_LINKED 0x80 |
| #define | NDEBUG_MAIN 0x100 |
| #define | NDEBUG_NO_DATAOUT 0x200 |
| #define | NDEBUG_NO_WRITE 0x400 |
| #define | NDEBUG_PIO 0x800 |
| #define | NDEBUG_PSEUDO_DMA 0x1000 |
| #define | NDEBUG_QUEUES 0x2000 |
| #define | NDEBUG_RESELECTION 0x4000 |
| #define | NDEBUG_SELECTION 0x8000 |
| #define | NDEBUG_USLEEP 0x10000 |
| #define | NDEBUG_LAST_BYTE_SENT 0x20000 |
| #define | NDEBUG_RESTART_SELECT 0x40000 |
| #define | NDEBUG_EXTENDED 0x80000 |
| #define | NDEBUG_C400_PREAD 0x100000 |
| #define | NDEBUG_C400_PWRITE 0x200000 |
| #define | NDEBUG_LISTS 0x400000 |
| #define | NDEBUG_ANY 0xFFFFFFFFUL |
| #define | OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */ |
| #define | CURRENT_SCSI_DATA_REG 0 /* ro same */ |
| #define | INITIATOR_COMMAND_REG 1 /* rw */ |
| #define | ICR_ASSERT_RST 0x80 /* rw Set to assert RST */ |
| #define | ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */ |
| #define | ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */ |
| #define | ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */ |
| #define | ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */ |
| #define | ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */ |
| #define | ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */ |
| #define | ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */ |
| #define | ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */ |
| #define | ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */ |
| #define | ICR_BASE 0 |
| #define | MODE_REG 2 |
| #define | MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */ |
| #define | MR_TARGET 0x40 /* rw target mode */ |
| #define | MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */ |
| #define | MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */ |
| #define | MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */ |
| #define | MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */ |
| #define | MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */ |
| #define | MR_ARBITRATE 0x01 /* rw start arbitration */ |
| #define | MR_BASE 0 |
| #define | TARGET_COMMAND_REG 3 |
| #define | TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */ |
| #define | TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */ |
| #define | TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */ |
| #define | TCR_ASSERT_CD 0x02 /* tgt rw assert CD */ |
| #define | TCR_ASSERT_IO 0x01 /* tgt rw assert IO */ |
| #define | STATUS_REG 4 /* ro */ |
| #define | SR_RST 0x80 |
| #define | SR_BSY 0x40 |
| #define | SR_REQ 0x20 |
| #define | SR_MSG 0x10 |
| #define | SR_CD 0x08 |
| #define | SR_IO 0x04 |
| #define | SR_SEL 0x02 |
| #define | SR_DBP 0x01 |
| #define | SELECT_ENABLE_REG 4 /* wo */ |
| #define | BUS_AND_STATUS_REG 5 /* ro */ |
| #define | BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */ |
| #define | BASR_DRQ 0x40 /* ro mirror of DRQ pin */ |
| #define | BASR_PARITY_ERROR 0x20 /* ro parity error detected */ |
| #define | BASR_IRQ 0x10 /* ro mirror of IRQ pin */ |
| #define | BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */ |
| #define | BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */ |
| #define | BASR_ATN 0x02 /* ro BUS status */ |
| #define | BASR_ACK 0x01 /* ro BUS status */ |
| #define | START_DMA_SEND_REG 5 /* wo */ |
| #define | INPUT_DATA_REG 6 /* ro */ |
| #define | START_DMA_TARGET_RECEIVE_REG 6 /* wo */ |
| #define | RESET_PARITY_INTERRUPT_REG 7 /* ro */ |
| #define | START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */ |
| #define | C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */ |
| #define | CSR_RESET 0x80 /* wo Resets 53c400 */ |
| #define | CSR_53C80_REG 0x80 /* ro 5380 registers busy */ |
| #define | CSR_TRANS_DIR 0x40 /* rw Data transfer direction */ |
| #define | CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */ |
| #define | CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */ |
| #define | CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */ |
| #define | CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */ |
| #define | CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */ |
| #define | CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */ |
| #define | CSR_BASE CSR_53C80_INTR |
| #define | C400_BLOCK_COUNTER_REG NCR53C400_register_offset-7 /* rw */ |
| #define | C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6 /* wo */ |
| #define | C400_HOST_BUFFER NCR53C400_register_offset-4 /* rw */ |
| #define | PHASE_MASK (SR_MSG | SR_CD | SR_IO) |
| #define | PHASE_DATAOUT 0 |
| #define | PHASE_DATAIN SR_IO |
| #define | PHASE_CMDOUT SR_CD |
| #define | PHASE_STATIN (SR_CD | SR_IO) |
| #define | PHASE_MSGOUT (SR_MSG | SR_CD) |
| #define | PHASE_MSGIN (SR_MSG | SR_CD | SR_IO) |
| #define | PHASE_UNKNOWN 0xff |
| #define | PHASE_SR_TO_TCR(phase) ((phase) >> 2) |
| #define | DISCONNECT_NONE 0 |
| #define | DISCONNECT_TIME_TO_DATA 1 |
| #define | DISCONNECT_LONG 2 |
| #define | TAG_NEXT -1 /* Use next free tag */ |
| #define | TAG_NONE |
| #define | SCSI_IRQ_NONE 255 |
| #define | DMA_NONE 255 |
| #define | IRQ_AUTO 254 |
| #define | DMA_AUTO 254 |
| #define | PORT_AUTO 0xffff /* autoprobe io port for 53c400a */ |
| #define | FLAG_HAS_LAST_BYTE_SENT 1 /* NCR53c81 or better */ |
| #define | FLAG_CHECK_LAST_BYTE_SENT 2 /* Only test once */ |
| #define | FLAG_NCR53C400 4 /* NCR53c400 */ |
| #define | FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */ |
| #define | FLAG_DTC3181E 16 /* DTC3181E */ |
| #define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */ |
| #define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */ |
| #define BASR_PARITY_ERROR 0x20 /* ro parity error detected */ |
| #define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */ |
| #define C400_BLOCK_COUNTER_REG NCR53C400_register_offset-7 /* rw */ |
| #define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */ |
| #define C400_HOST_BUFFER NCR53C400_register_offset-4 /* rw */ |
| #define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6 /* wo */ |
| #define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */ |
| #define CSR_BASE CSR_53C80_INTR |
| #define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */ |
| #define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */ |
| #define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */ |
| #define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */ |
| #define FLAG_HAS_LAST_BYTE_SENT 1 /* NCR53c81 or better */ |
| #define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */ |
| #define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */ |
| #define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */ |
| #define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */ |
| #define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */ |
| #define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */ |
| #define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */ |
| #define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */ |
| #define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */ |
| #define PORT_AUTO 0xffff /* autoprobe io port for 53c400a */ |
| #define TAG_NONE |
1.8.2