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#define | AD5933_REG_CONTROL_HB 0x80 /* R/W, 2 bytes */ |
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#define | AD5933_REG_CONTROL_LB 0x81 /* R/W, 2 bytes */ |
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#define | AD5933_REG_FREQ_START 0x82 /* R/W, 3 bytes */ |
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#define | AD5933_REG_FREQ_INC 0x85 /* R/W, 3 bytes */ |
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#define | AD5933_REG_INC_NUM 0x88 /* R/W, 2 bytes, 9 bit */ |
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#define | AD5933_REG_SETTLING_CYCLES 0x8A /* R/W, 2 bytes */ |
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#define | AD5933_REG_STATUS 0x8F /* R, 1 byte */ |
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#define | AD5933_REG_TEMP_DATA 0x92 /* R, 2 bytes*/ |
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#define | AD5933_REG_REAL_DATA 0x94 /* R, 2 bytes*/ |
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#define | AD5933_REG_IMAG_DATA 0x96 /* R, 2 bytes*/ |
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#define | AD5933_CTRL_INIT_START_FREQ (0x1 << 4) |
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#define | AD5933_CTRL_START_SWEEP (0x2 << 4) |
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#define | AD5933_CTRL_INC_FREQ (0x3 << 4) |
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#define | AD5933_CTRL_REPEAT_FREQ (0x4 << 4) |
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#define | AD5933_CTRL_MEASURE_TEMP (0x9 << 4) |
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#define | AD5933_CTRL_POWER_DOWN (0xA << 4) |
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#define | AD5933_CTRL_STANDBY (0xB << 4) |
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#define | AD5933_CTRL_RANGE_2000mVpp (0x0 << 1) |
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#define | AD5933_CTRL_RANGE_200mVpp (0x1 << 1) |
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#define | AD5933_CTRL_RANGE_400mVpp (0x2 << 1) |
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#define | AD5933_CTRL_RANGE_1000mVpp (0x3 << 1) |
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#define | AD5933_CTRL_RANGE(x) ((x) << 1) |
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#define | AD5933_CTRL_PGA_GAIN_1 (0x1 << 0) |
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#define | AD5933_CTRL_PGA_GAIN_5 (0x0 << 0) |
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#define | AD5933_CTRL_RESET (0x1 << 4) |
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#define | AD5933_CTRL_INT_SYSCLK (0x0 << 3) |
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#define | AD5933_CTRL_EXT_SYSCLK (0x1 << 3) |
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#define | AD5933_STAT_TEMP_VALID (0x1 << 0) |
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#define | AD5933_STAT_DATA_VALID (0x1 << 1) |
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#define | AD5933_STAT_SWEEP_DONE (0x1 << 2) |
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#define | AD5933_I2C_BLOCK_WRITE 0xA0 |
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#define | AD5933_I2C_BLOCK_READ 0xA1 |
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#define | AD5933_I2C_ADDR_POINTER 0xB0 |
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#define | AD5933_INT_OSC_FREQ_Hz 16776000 |
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#define | AD5933_MAX_OUTPUT_FREQ_Hz 100000 |
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#define | AD5933_MAX_RETRIES 100 |
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#define | AD5933_OUT_RANGE 1 |
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#define | AD5933_OUT_RANGE_AVAIL 2 |
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#define | AD5933_OUT_SETTLING_CYCLES 3 |
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#define | AD5933_IN_PGA_GAIN 4 |
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#define | AD5933_IN_PGA_GAIN_AVAIL 5 |
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#define | AD5933_FREQ_POINTS 6 |
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#define | AD5933_POLL_TIME_ms 10 |
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#define | AD5933_INIT_EXCITATION_TIME_ms 100 |
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