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24 #define G2_FIFO 0xa05f688c
25 #define SPU_MEMORY_BASE 0xA0800000
26 #define ARM_RESET_REGISTER 0xA0702C00
27 #define SPU_REGISTER_BASE 0xA0700000
30 #define AICA_CONTROL_POINT 0xA0810000
31 #define AICA_CONTROL_CHANNEL_SAMPLE_NUMBER 0xA0810008
32 #define AICA_CHANNEL0_CONTROL_OFFSET 0x10004
35 #define AICA_CMD_KICK 0x80000000
36 #define AICA_CMD_NONE 0
37 #define AICA_CMD_START 1
38 #define AICA_CMD_STOP 2
39 #define AICA_CMD_VOL 3
47 #define AICA_BUFFER_SIZE 0x8000
48 #define AICA_PERIOD_SIZE 0x800
49 #define AICA_PERIOD_NUMBER 16
51 #define AICA_CHANNEL0_OFFSET 0x11000
52 #define AICA_CHANNEL1_OFFSET 0x21000
53 #define CHANNEL_OFFSET 0x10000
55 #define AICA_DMA_CHANNEL 5
56 #define AICA_DMA_MODE 5
58 #define SND_AICA_DRIVER "AICA"