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#define AICA_BUFFER_SIZE 0x8000 |
#define AICA_CHANNEL0_CONTROL_OFFSET 0x10004 |
#define AICA_CHANNEL0_OFFSET 0x11000 |
#define AICA_CHANNEL1_OFFSET 0x21000 |
#define AICA_CMD_KICK 0x80000000 |
#define AICA_CONTROL_CHANNEL_SAMPLE_NUMBER 0xA0810008 |
#define AICA_CONTROL_POINT 0xA0810000 |
#define AICA_DMA_CHANNEL 5 |
#define AICA_PERIOD_NUMBER 16 |
#define AICA_PERIOD_SIZE 0x800 |
#define ARM_RESET_REGISTER 0xA0702C00 |
#define CHANNEL_OFFSET 0x10000 |
#define G2_FIFO 0xa05f688c |
#define SND_AICA_DRIVER "AICA" |
#define SPU_MEMORY_BASE 0xA0800000 |
#define SPU_REGISTER_BASE 0xA0700000 |