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ali-ircc.h
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1 /*********************************************************************
2  *
3  * Filename: ali-ircc.h
4  * Version: 0.5
5  * Description: Driver for the ALI M1535D and M1543C FIR Controller
6  * Status: Experimental.
7  * Author: Benjamin Kong <[email protected]>
8  * Created at: 2000/10/16 03:46PM
9  * Modified at: 2001/1/3 02:56PM
10  * Modified by: Benjamin Kong <[email protected]>
11  *
12  * Copyright (c) 2000 Benjamin Kong <[email protected]>
13  * All Rights Reserved
14  *
15  * This program is free software; you can redistribute it and/or
16  * modify it under the terms of the GNU General Public License as
17  * published by the Free Software Foundation; either version 2 of
18  * the License, or (at your option) any later version.
19  *
20  ********************************************************************/
21 
22 #ifndef ALI_IRCC_H
23 #define ALI_IRCC_H
24 
25 #include <linux/time.h>
26 
27 #include <linux/spinlock.h>
28 #include <linux/pm.h>
29 #include <linux/types.h>
30 #include <asm/io.h>
31 
32 /* SIR Register */
33 /* Usr definition of linux/serial_reg.h */
34 
35 /* FIR Register */
36 #define BANK0 0x20
37 #define BANK1 0x21
38 #define BANK2 0x22
39 #define BANK3 0x23
40 
41 #define FIR_MCR 0x07 /* Master Control Register */
42 
43 /* Bank 0 */
44 #define FIR_DR 0x00 /* Alias 0, FIR Data Register (R/W) */
45 #define FIR_IER 0x01 /* Alias 1, FIR Interrupt Enable Register (R/W) */
46 #define FIR_IIR 0x02 /* Alias 2, FIR Interrupt Identification Register (Read only) */
47 #define FIR_LCR_A 0x03 /* Alias 3, FIR Line Control Register A (R/W) */
48 #define FIR_LCR_B 0x04 /* Alias 4, FIR Line Control Register B (R/W) */
49 #define FIR_LSR 0x05 /* Alias 5, FIR Line Status Register (R/W) */
50 #define FIR_BSR 0x06 /* Alias 6, FIR Bus Status Register (Read only) */
51 
52 
53  /* Alias 1 */
54  #define IER_FIFO 0x10 /* FIR FIFO Interrupt Enable */
55  #define IER_TIMER 0x20 /* Timer Interrupt Enable */
56  #define IER_EOM 0x40 /* End of Message Interrupt Enable */
57  #define IER_ACT 0x80 /* Active Frame Interrupt Enable */
58 
59  /* Alias 2 */
60  #define IIR_FIFO 0x10 /* FIR FIFO Interrupt */
61  #define IIR_TIMER 0x20 /* Timer Interrupt */
62  #define IIR_EOM 0x40 /* End of Message Interrupt */
63  #define IIR_ACT 0x80 /* Active Frame Interrupt */
64 
65  /* Alias 3 */
66  #define LCR_A_FIFO_RESET 0x80 /* FIFO Reset */
67 
68  /* Alias 4 */
69  #define LCR_B_BW 0x10 /* Brick Wall */
70  #define LCR_B_SIP 0x20 /* SIP Enable */
71  #define LCR_B_TX_MODE 0x40 /* Transmit Mode */
72  #define LCR_B_RX_MODE 0x80 /* Receive Mode */
73 
74  /* Alias 5 */
75  #define LSR_FIR_LSA 0x00 /* FIR Line Status Address */
76  #define LSR_FRAME_ABORT 0x08 /* Frame Abort */
77  #define LSR_CRC_ERROR 0x10 /* CRC Error */
78  #define LSR_SIZE_ERROR 0x20 /* Size Error */
79  #define LSR_FRAME_ERROR 0x40 /* Frame Error */
80  #define LSR_FIFO_UR 0x80 /* FIFO Underrun */
81  #define LSR_FIFO_OR 0x80 /* FIFO Overrun */
82 
83  /* Alias 6 */
84  #define BSR_FIFO_NOT_EMPTY 0x80 /* FIFO Not Empty */
85 
86 /* Bank 1 */
87 #define FIR_CR 0x00 /* Alias 0, FIR Configuration Register (R/W) */
88 #define FIR_FIFO_TR 0x01 /* Alias 1, FIR FIFO Threshold Register (R/W) */
89 #define FIR_DMA_TR 0x02 /* Alias 2, FIR DMA Threshold Register (R/W) */
90 #define FIR_TIMER_IIR 0x03 /* Alias 3, FIR Timer interrupt interval register (W/O) */
91 #define FIR_FIFO_FR 0x03 /* Alias 3, FIR FIFO Flag register (R/O) */
92 #define FIR_FIFO_RAR 0x04 /* Alias 4, FIR FIFO Read Address register (R/O) */
93 #define FIR_FIFO_WAR 0x05 /* Alias 5, FIR FIFO Write Address register (R/O) */
94 #define FIR_TR 0x06 /* Alias 6, Test REgister (W/O) */
95 
96  /* Alias 0 */
97  #define CR_DMA_EN 0x01 /* DMA Enable */
98  #define CR_DMA_BURST 0x02 /* DMA Burst Mode */
99  #define CR_TIMER_EN 0x08 /* Timer Enable */
100 
101  /* Alias 3 */
102  #define TIMER_IIR_500 0x00 /* 500 us */
103  #define TIMER_IIR_1ms 0x01 /* 1 ms */
104  #define TIMER_IIR_2ms 0x02 /* 2 ms */
105  #define TIMER_IIR_4ms 0x03 /* 4 ms */
106 
107 /* Bank 2 */
108 #define FIR_IRDA_CR 0x00 /* Alias 0, IrDA Control Register (R/W) */
109 #define FIR_BOF_CR 0x01 /* Alias 1, BOF Count Register (R/W) */
110 #define FIR_BW_CR 0x02 /* Alias 2, Brick Wall Count Register (R/W) */
111 #define FIR_TX_DSR_HI 0x03 /* Alias 3, TX Data Size Register (high) (R/W) */
112 #define FIR_TX_DSR_LO 0x04 /* Alias 4, TX Data Size Register (low) (R/W) */
113 #define FIR_RX_DSR_HI 0x05 /* Alias 5, RX Data Size Register (high) (R/W) */
114 #define FIR_RX_DSR_LO 0x06 /* Alias 6, RX Data Size Register (low) (R/W) */
115 
116  /* Alias 0 */
117  #define IRDA_CR_HDLC1152 0x80 /* 1.152Mbps HDLC Select */
118  #define IRDA_CR_CRC 0X40 /* CRC Select. */
119  #define IRDA_CR_HDLC 0x20 /* HDLC select. */
120  #define IRDA_CR_HP_MODE 0x10 /* HP mode (read only) */
121  #define IRDA_CR_SD_ST 0x08 /* SD/MODE State. */
122  #define IRDA_CR_FIR_SIN 0x04 /* FIR SIN Select. */
123  #define IRDA_CR_ITTX_0 0x02 /* SOUT State. IRTX force to 0 */
124  #define IRDA_CR_ITTX_1 0x03 /* SOUT State. IRTX force to 1 */
125 
126 /* Bank 3 */
127 #define FIR_ID_VR 0x00 /* Alias 0, FIR ID Version Register (R/O) */
128 #define FIR_MODULE_CR 0x01 /* Alias 1, FIR Module Control Register (R/W) */
129 #define FIR_IO_BASE_HI 0x02 /* Alias 2, FIR Higher I/O Base Address Register (R/O) */
130 #define FIR_IO_BASE_LO 0x03 /* Alias 3, FIR Lower I/O Base Address Register (R/O) */
131 #define FIR_IRQ_CR 0x04 /* Alias 4, FIR IRQ Channel Register (R/O) */
132 #define FIR_DMA_CR 0x05 /* Alias 5, FIR DMA Channel Register (R/O) */
133 
134 struct ali_chip {
135  char *name;
136  int cfg[2];
137  unsigned char entr1;
138  unsigned char entr2;
139  unsigned char cid_index;
140  unsigned char cid_value;
141  int (*probe)(struct ali_chip *chip, chipio_t *info);
142  int (*init)(struct ali_chip *chip, chipio_t *info);
143 };
144 typedef struct ali_chip ali_chip_t;
145 
146 
147 /* DMA modes needed */
148 #define DMA_TX_MODE 0x08 /* Mem to I/O, ++, demand. */
149 #define DMA_RX_MODE 0x04 /* I/O to mem, ++, demand. */
150 
151 #define MAX_TX_WINDOW 7
152 #define MAX_RX_WINDOW 7
153 
154 #define TX_FIFO_Threshold 8
155 #define RX_FIFO_Threshold 1
156 #define TX_DMA_Threshold 1
157 #define RX_DMA_Threshold 1
158 
159 /* For storing entries in the status FIFO */
160 
161 struct st_fifo_entry {
162  int status;
163  int len;
164 };
165 
166 struct st_fifo {
167  struct st_fifo_entry entries[MAX_RX_WINDOW];
168  int pending_bytes;
169  int head;
170  int tail;
171  int len;
172 };
173 
174 struct frame_cb {
175  void *start; /* Start of frame in DMA mem */
176  int len; /* Length of frame in DMA mem */
177 };
178 
179 struct tx_fifo {
180  struct frame_cb queue[MAX_TX_WINDOW]; /* Info about frames in queue */
181  int ptr; /* Currently being sent */
182  int len; /* Length of queue */
183  int free; /* Next free slot */
184  void *tail; /* Next free start in DMA mem */
185 };
186 
187 /* Private data for each instance */
188 struct ali_ircc_cb {
189 
190  struct st_fifo st_fifo; /* Info about received frames */
191  struct tx_fifo tx_fifo; /* Info about frames to be transmitted */
192 
193  struct net_device *netdev; /* Yes! we are some kind of netdevice */
194 
195  struct irlap_cb *irlap; /* The link layer we are binded to */
196  struct qos_info qos; /* QoS capabilities for this device */
197 
198  chipio_t io; /* IrDA controller information */
199  iobuff_t tx_buff; /* Transmit buffer */
200  iobuff_t rx_buff; /* Receive buffer */
201  dma_addr_t tx_buff_dma;
202  dma_addr_t rx_buff_dma;
203 
204  __u8 ier; /* Interrupt enable register */
205 
206  __u8 InterruptID; /* Interrupt ID */
207  __u8 BusStatus; /* Bus Status */
208  __u8 LineStatus; /* Line Status */
209 
210  unsigned char rcvFramesOverflow;
211 
212  struct timeval stamp;
213  struct timeval now;
214 
215  spinlock_t lock; /* For serializing operations */
216 
217  __u32 new_speed;
218  int index; /* Instance index */
219 
220  unsigned char fifo_opti_buf;
221 };
222 
223 static inline void switch_bank(int iobase, int bank)
224 {
225  outb(bank, iobase+FIR_MCR);
226 }
227 
228 #endif /* ALI_IRCC_H */
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