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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Data Structures | |
| struct | amd8111e_tx_dr |
| struct | amd8111e_rx_dr |
| struct | amd8111e_link_config |
| struct | amd8111e_coalesce_conf |
| struct | ipg_info |
| struct | amd8111e_priv |
Macros | |
| #define | ASF_STAT 0x00 /* ASF status register */ |
| #define | CHIPID 0x04 /* Chip ID regsiter */ |
| #define | MIB_DATA 0x10 /* MIB data register */ |
| #define | MIB_ADDR 0x14 /* MIB address register */ |
| #define | STAT0 0x30 /* Status0 register */ |
| #define | INT0 0x38 /* Interrupt0 register */ |
| #define | INTEN0 0x40 /* Interrupt0 enable register*/ |
| #define | CMD0 0x48 /* Command0 register */ |
| #define | CMD2 0x50 /* Command2 register */ |
| #define | CMD3 0x54 /* Command3 resiter */ |
| #define | CMD7 0x64 /* Command7 register */ |
| #define | CTRL1 0x6C /* Control1 register */ |
| #define | CTRL2 0x70 /* Control2 register */ |
| #define | XMT_RING_LIMIT 0x7C /* Transmit ring limit register */ |
| #define | AUTOPOLL0 0x88 /* Auto-poll0 register */ |
| #define | AUTOPOLL1 0x8A /* Auto-poll1 register */ |
| #define | AUTOPOLL2 0x8C /* Auto-poll2 register */ |
| #define | AUTOPOLL3 0x8E /* Auto-poll3 register */ |
| #define | AUTOPOLL4 0x90 /* Auto-poll4 register */ |
| #define | AUTOPOLL5 0x92 /* Auto-poll5 register */ |
| #define | AP_VALUE 0x98 /* Auto-poll value register */ |
| #define | DLY_INT_A 0xA8 /* Group A delayed interrupt register */ |
| #define | DLY_INT_B 0xAC /* Group B delayed interrupt register */ |
| #define | FLOW_CONTROL 0xC8 /* Flow control register */ |
| #define | PHY_ACCESS 0xD0 /* PHY access register */ |
| #define | STVAL 0xD8 /* Software timer value register */ |
| #define | XMT_RING_BASE_ADDR0 0x100 /* Transmit ring0 base addr register */ |
| #define | XMT_RING_BASE_ADDR1 0x108 /* Transmit ring1 base addr register */ |
| #define | XMT_RING_BASE_ADDR2 0x110 /* Transmit ring2 base addr register */ |
| #define | XMT_RING_BASE_ADDR3 0x118 /* Transmit ring2 base addr register */ |
| #define | RCV_RING_BASE_ADDR0 0x120 /* Transmit ring0 base addr register */ |
| #define | PMAT0 0x190 /* OnNow pattern register0 */ |
| #define | PMAT1 0x194 /* OnNow pattern register1 */ |
| #define | XMT_RING_LEN0 0x140 /* Transmit Ring0 length register */ |
| #define | XMT_RING_LEN1 0x144 /* Transmit Ring1 length register */ |
| #define | XMT_RING_LEN2 0x148 /* Transmit Ring2 length register */ |
| #define | XMT_RING_LEN3 0x14C /* Transmit Ring3 length register */ |
| #define | RCV_RING_LEN0 0x150 /* Receive Ring0 length register */ |
| #define | SRAM_SIZE 0x178 /* SRAM size register */ |
| #define | SRAM_BOUNDARY 0x17A /* SRAM boundary register */ |
| #define | PADR 0x160 /* Physical address register */ |
| #define | IFS1 0x18C /* Inter-frame spacing Part1 register */ |
| #define | IFS 0x18D /* Inter-frame spacing register */ |
| #define | IPG 0x18E /* Inter-frame gap register */ |
| #define | LADRF 0x168 /* Logical address filter register */ |
| #define | PHY_SPEED_10 0x2 |
| #define | PHY_SPEED_100 0x3 |
| #define | rcv_miss_pkts 0x00 |
| #define | rcv_octets 0x01 |
| #define | rcv_broadcast_pkts 0x02 |
| #define | rcv_multicast_pkts 0x03 |
| #define | rcv_undersize_pkts 0x04 |
| #define | rcv_oversize_pkts 0x05 |
| #define | rcv_fragments 0x06 |
| #define | rcv_jabbers 0x07 |
| #define | rcv_unicast_pkts 0x08 |
| #define | rcv_alignment_errors 0x09 |
| #define | rcv_fcs_errors 0x0A |
| #define | rcv_good_octets 0x0B |
| #define | rcv_mac_ctrl 0x0C |
| #define | rcv_flow_ctrl 0x0D |
| #define | rcv_pkts_64_octets 0x0E |
| #define | rcv_pkts_65to127_octets 0x0F |
| #define | rcv_pkts_128to255_octets 0x10 |
| #define | rcv_pkts_256to511_octets 0x11 |
| #define | rcv_pkts_512to1023_octets 0x12 |
| #define | rcv_pkts_1024to1518_octets 0x13 |
| #define | rcv_unsupported_opcode 0x14 |
| #define | rcv_symbol_errors 0x15 |
| #define | rcv_drop_pkts_ring1 0x16 |
| #define | rcv_drop_pkts_ring2 0x17 |
| #define | rcv_drop_pkts_ring3 0x18 |
| #define | rcv_drop_pkts_ring4 0x19 |
| #define | rcv_jumbo_pkts 0x1A |
| #define | xmt_underrun_pkts 0x20 |
| #define | xmt_octets 0x21 |
| #define | xmt_packets 0x22 |
| #define | xmt_broadcast_pkts 0x23 |
| #define | xmt_multicast_pkts 0x24 |
| #define | xmt_collisions 0x25 |
| #define | xmt_unicast_pkts 0x26 |
| #define | xmt_one_collision 0x27 |
| #define | xmt_multiple_collision 0x28 |
| #define | xmt_deferred_transmit 0x29 |
| #define | xmt_late_collision 0x2A |
| #define | xmt_excessive_defer 0x2B |
| #define | xmt_loss_carrier 0x2C |
| #define | xmt_excessive_collision 0x2D |
| #define | xmt_back_pressure 0x2E |
| #define | xmt_flow_ctrl 0x2F |
| #define | xmt_pkts_64_octets 0x30 |
| #define | xmt_pkts_65to127_octets 0x31 |
| #define | xmt_pkts_128to255_octets 0x32 |
| #define | xmt_pkts_256to511_octets 0x33 |
| #define | xmt_pkts_512to1023_octets 0x34 |
| #define | xmt_pkts_1024to1518_octet 0x35 |
| #define | xmt_oversize_pkts 0x36 |
| #define | xmt_jumbo_pkts 0x37 |
| #define | PCI_VENDOR_ID_AMD 0x1022 |
| #define | PCI_DEVICE_ID_AMD8111E_7462 0x7462 |
| #define | MAX_UNITS 8 /* Maximum number of devices possible */ |
| #define | NUM_TX_BUFFERS 32 /* Number of transmit buffers */ |
| #define | NUM_RX_BUFFERS 32 /* Number of receive buffers */ |
| #define | TX_BUFF_MOD_MASK 31 /* (NUM_TX_BUFFERS -1) */ |
| #define | RX_BUFF_MOD_MASK 31 /* (NUM_RX_BUFFERS -1) */ |
| #define | NUM_TX_RING_DR 32 |
| #define | NUM_RX_RING_DR 32 |
| #define | TX_RING_DR_MOD_MASK 31 /* (NUM_TX_RING_DR -1) */ |
| #define | RX_RING_DR_MOD_MASK 31 /* (NUM_RX_RING_DR -1) */ |
| #define | MAX_FILTER_SIZE 64 /* Maximum multicast address */ |
| #define | AMD8111E_MIN_MTU 60 |
| #define | AMD8111E_MAX_MTU 9000 |
| #define | PKT_BUFF_SZ 1536 |
| #define | MIN_PKT_LEN 60 |
| #define | AMD8111E_TX_TIMEOUT (3 * HZ)/* 3 sec */ |
| #define | SOFT_TIMER_FREQ 0xBEBC /* 0.5 sec */ |
| #define | DELAY_TIMER_CONV |
| #define | OPTION_VLAN_ENABLE 0x0001 |
| #define | OPTION_JUMBO_ENABLE 0x0002 |
| #define | OPTION_MULTICAST_ENABLE 0x0004 |
| #define | OPTION_WOL_ENABLE 0x0008 |
| #define | OPTION_WAKE_MAGIC_ENABLE 0x0010 |
| #define | OPTION_WAKE_PHY_ENABLE 0x0020 |
| #define | OPTION_INTR_COAL_ENABLE 0x0040 |
| #define | OPTION_DYN_IPG_ENABLE 0x0080 |
| #define | PHY_REG_ADDR_MASK 0x1f |
| #define | DEFAULT_IPG 0x60 |
| #define | IFS1_DELTA 36 |
| #define | IPG_CONVERGE_JIFFIES (HZ/2) |
| #define | IPG_STABLE_TIME 5 |
| #define | MIN_IPG 96 |
| #define | MAX_IPG 255 |
| #define | IPG_STEP 16 |
| #define | CSTATE 1 |
| #define | SSTATE 2 |
| #define | REPEAT_CNT 10 |
| #define | RESET_RX_FLAGS 0x0000 |
| #define | TT_MASK 0x000c |
| #define | TCC_MASK 0x0003 |
| #define | AMD8111E_REG_DUMP_LEN 13*sizeof(u32) |
| #define | SPEED_INVALID 0xffff |
| #define | DUPLEX_INVALID 0xff |
| #define | AUTONEG_INVALID 0xff |
| #define | MAX_TIMEOUT 40 |
| #define | MAX_EVENT_COUNT 31 |
| #define | amd8111e_writeq(_UlData, _memMap) |
Enumerations | |
| enum | STAT_ASF_BITS { ASF_INIT_DONE = (1 << 1), ASF_INIT_PRESENT = (1 << 0) } |
| enum | MIB_ADDR_BITS { MIB_CMD_ACTIVE = (1 << 15 ), MIB_RD_CMD = (1 << 13 ), MIB_CLEAR = (1 << 12 ), MIB_ADDRESS } |
| enum | STAT0_BITS { PMAT_DET = (1 << 12), MP_DET = (1 << 11), LC_DET = (1 << 10), SPEED_MASK = (1 << 9)|(1 << 8)|(1 << 7), FULL_DPLX = (1 << 6), LINK_STATS = (1 << 5), AUTONEG_COMPLETE = (1 << 4), MIIPD = (1 << 3), RX_SUSPENDED = (1 << 2), TX_SUSPENDED = (1 << 1), RUNNING = (1 << 0) } |
| enum | INT0_BITS { INTR = (1 << 31), PCSINT = (1 << 28), LCINT = (1 << 27), APINT5 = (1 << 26), APINT4 = (1 << 25), APINT3 = (1 << 24), TINT_SUM = (1 << 23), APINT2 = (1 << 22), APINT1 = (1 << 21), APINT0 = (1 << 20), MIIPDTINT = (1 << 19), MCCINT = (1 << 17), MREINT = (1 << 16), RINT_SUM = (1 << 15), SPNDINT = (1 << 14), MPINT = (1 << 13), SINT = (1 << 12), TINT3 = (1 << 11), TINT2 = (1 << 10), TINT1 = (1 << 9), TINT0 = (1 << 8), UINT = (1 << 7), STINT = (1 << 4), RINT0 = (1 << 0) } |
| enum | VAL_BITS { VAL3 = (1 << 31), VAL2 = (1 << 23), VAL1 = (1 << 15), VAL0 = (1 << 7) } |
| enum | INTEN0_BITS { LCINTEN = (1 << 27), APINT5EN = (1 << 26), APINT4EN = (1 << 25), APINT3EN = (1 << 24), APINT2EN = (1 << 22), APINT1EN = (1 << 21), APINT0EN = (1 << 20), MIIPDTINTEN = (1 << 19), MCCIINTEN = (1 << 18), MCCINTEN = (1 << 17), MREINTEN = (1 << 16), SPNDINTEN = (1 << 14), MPINTEN = (1 << 13), TINTEN3 = (1 << 11), SINTEN = (1 << 12), TINTEN2 = (1 << 10), TINTEN1 = (1 << 9), TINTEN0 = (1 << 8), STINTEN = (1 << 4), RINTEN0 = (1 << 0), INTEN0_CLEAR = 0x1F7F7F1F } |
| enum | CMD0_BITS { RDMD0 = (1 << 16), TDMD3 = (1 << 11), TDMD2 = (1 << 10), TDMD1 = (1 << 9), TDMD0 = (1 << 8), UINTCMD = (1 << 6), RX_FAST_SPND = (1 << 5), TX_FAST_SPND = (1 << 4), RX_SPND = (1 << 3), TX_SPND = (1 << 2), INTREN = (1 << 1), RUN = (1 << 0), CMD0_CLEAR = 0x000F0F7F } |
| enum | CMD2_BITS { CONDUIT_MODE = (1 << 29), RPA = (1 << 19), DRCVPA = (1 << 18), DRCVBC = (1 << 17), PROM = (1 << 16), ASTRP_RCV = (1 << 13), RCV_DROP0 = (1 << 12), EMBA = (1 << 11), DXMT2PD = (1 << 10), LTINTEN = (1 << 9), DXMTFCS = (1 << 8), APAD_XMT = (1 << 6), DRTY = (1 << 5), INLOOP = (1 << 4), EXLOOP = (1 << 3), REX_RTRY = (1 << 2), REX_UFLO = (1 << 1), REX_LCOL = (1 << 0), CMD2_CLEAR = 0x3F7F3F7F } |
| enum | CMD3_BITS { ASF_INIT_DONE_ALIAS = (1 << 29), JUMBO = (1 << 21), VSIZE = (1 << 20), VLONLY = (1 << 19), VL_TAG_DEL = (1 << 18), EN_PMGR = (1 << 14), INTLEVEL = (1 << 13), FORCE_FULL_DUPLEX = (1 << 12), FORCE_LINK_STATUS = (1 << 11), APEP = (1 << 10), MPPLBA = (1 << 9), RESET_PHY_PULSE = (1 << 2), RESET_PHY = (1 << 1), PHY_RST_POL = (1 << 0) } |
| enum | CMD7_BITS { PMAT_SAVE_MATCH = (1 << 4), PMAT_MODE = (1 << 3), MPEN_SW = (1 << 1), LCMODE_SW = (1 << 0), CMD7_CLEAR = 0x0000001B } |
| enum | CTRL1_BITS { RESET_PHY_WIDTH = (0xF << 16) | (0xF<< 20), XMTSP_MASK = (1 << 9) | (1 << 8), XMTSP_128 = (1 << 9), XMTSP_64 = (1 << 8), CACHE_ALIGN = (1 << 4), BURST_LIMIT_MASK = (0xF << 0 ), CTRL1_DEFAULT = 0x00010111 } |
| enum | CTRL2_BITS { FMDC_MASK = (1 << 9)|(1 << 8), XPHYRST = (1 << 7), XPHYANE = (1 << 6), XPHYFD = (1 << 5), XPHYSP = (1 << 4) | (1 << 3), APDW_MASK = (1 << 2) | (1 << 1) | (1 << 0) } |
| enum | XMT_RING_LIMIT_BITS { XMT_RING2_LIMIT = (0xFF << 16), XMT_RING1_LIMIT = (0xFF << 8), XMT_RING0_LIMIT = (0xFF << 0) } |
| enum | AUTOPOLL0_BITS { AP_REG0_EN = (1 << 15), AP_REG0_ADDR_MASK = (0xF << 8) |(1 << 12), AP_PHY0_ADDR_MASK = (0xF << 0) |(1 << 4) } |
| enum | AUTOPOLL1_BITS { AP_REG1_EN = (1 << 15), AP_REG1_ADDR_MASK = (0xF << 8) |(1 << 12), AP_PRE_SUP1 = (1 << 6), AP_PHY1_DFLT = (1 << 5), AP_PHY1_ADDR_MASK = (0xF << 0) |(1 << 4) } |
| enum | AUTOPOLL2_BITS { AP_REG2_EN = (1 << 15), AP_REG2_ADDR_MASK = (0xF << 8) |(1 << 12), AP_PRE_SUP2 = (1 << 6), AP_PHY2_DFLT = (1 << 5), AP_PHY2_ADDR_MASK = (0xF << 0) |(1 << 4) } |
| enum | AUTOPOLL3_BITS { AP_REG3_EN = (1 << 15), AP_REG3_ADDR_MASK = (0xF << 8) |(1 << 12), AP_PRE_SUP3 = (1 << 6), AP_PHY3_DFLT = (1 << 5), AP_PHY3_ADDR_MASK = (0xF << 0) |(1 << 4) } |
| enum | AUTOPOLL4_BITS { AP_REG4_EN = (1 << 15), AP_REG4_ADDR_MASK = (0xF << 8) |(1 << 12), AP_PRE_SUP4 = (1 << 6), AP_PHY4_DFLT = (1 << 5), AP_PHY4_ADDR_MASK = (0xF << 0) |(1 << 4) } |
| enum | AUTOPOLL5_BITS { AP_REG5_EN = (1 << 15), AP_REG5_ADDR_MASK = (0xF << 8) |(1 << 12), AP_PRE_SUP5 = (1 << 6), AP_PHY5_DFLT = (1 << 5), AP_PHY5_ADDR_MASK = (0xF << 0) |(1 << 4) } |
| enum | AP_VALUE_BITS { AP_VAL_ACTIVE = (1 << 31), AP_VAL_RD_CMD = ( 1 << 29), AP_ADDR = (1 << 18)|(1 << 17)|(1 << 16), AP_VAL } |
| enum | DLY_INT_A_BITS { DLY_INT_A_R3 = (1 << 31), DLY_INT_A_R2 = (1 << 30), DLY_INT_A_R1 = (1 << 29), DLY_INT_A_R0 = (1 << 28), DLY_INT_A_T3 = (1 << 27), DLY_INT_A_T2 = (1 << 26), DLY_INT_A_T1 = (1 << 25), DLY_INT_A_T0 = ( 1 << 24), EVENT_COUNT_A = (0xF << 16) | (0x1 << 20), MAX_DELAY_TIME_A } |
| enum | DLY_INT_B_BITS { DLY_INT_B_R3 = (1 << 31), DLY_INT_B_R2 = (1 << 30), DLY_INT_B_R1 = (1 << 29), DLY_INT_B_R0 = (1 << 28), DLY_INT_B_T3 = (1 << 27), DLY_INT_B_T2 = (1 << 26), DLY_INT_B_T1 = (1 << 25), DLY_INT_B_T0 = ( 1 << 24), EVENT_COUNT_B = (0xF << 16) | (0x1 << 20), MAX_DELAY_TIME_B } |
| enum | FLOW_CONTROL_BITS { PAUSE_LEN_CHG = (1 << 30), FTPE = (1 << 22), FRPE = (1 << 21), NAPA = (1 << 20), NPA = (1 << 19), FIXP = ( 1 << 18), FCCMD = ( 1 << 16), PAUSE_LEN = (0xF << 0) | (0xF << 4) |( 0xF << 8) | (0xF << 12) } |
| enum | PHY_ACCESS_BITS { PHY_CMD_ACTIVE = (1 << 31), PHY_WR_CMD = (1 << 30), PHY_RD_CMD = (1 << 29), PHY_RD_ERR = (1 << 28), PHY_PRE_SUP = (1 << 27), PHY_ADDR, PHY_REG_ADDR = (1 << 16) | (1 << 17) | (1 << 18)| (1 << 19) | (1 << 20), PHY_DATA } |
| enum | PMAT0_BITS { PMR_ACTIVE = (1 << 31), PMR_WR_CMD = (1 << 30), PMR_RD_CMD = (1 << 29), PMR_BANK = (1 <<28), PMR_ADDR, PMR_B4 = (0xF << 0) | (0xF << 4) } |
| enum | PMAT1_BITS { PMR_B3 = (0xF << 24) | (0xF <<28), PMR_B2 = (0xF << 16) |(0xF << 20), PMR_B1 = (0xF << 8) | (0xF <<12), PMR_B0 = (0xF << 0)|(0xF << 4) } |
| enum | TX_FLAG_BITS { OWN_BIT = (1 << 15), ADD_FCS_BIT = (1 << 13), LTINT_BIT = (1 << 12), STP_BIT = (1 << 9), ENP_BIT = (1 << 8), KILL_BIT = (1 << 6), TCC_VLAN_INSERT = (1 << 1), TCC_VLAN_REPLACE = (1 << 1) |( 1<< 0) } |
| enum | RX_FLAG_BITS { ERR_BIT = (1 << 14), FRAM_BIT = (1 << 13), OFLO_BIT = (1 << 12), CRC_BIT = (1 << 11), PAM_BIT = (1 << 6), LAFM_BIT = (1 << 5), BAM_BIT = (1 << 4), TT_VLAN_TAGGED = (1 << 3) |(1 << 2), TT_PRTY_TAGGED = (1 << 3) } |
| enum | coal_type { NO_COALESCE, LOW_COALESCE, MEDIUM_COALESCE, HIGH_COALESCE } |
| enum | coal_mode { RX_INTR_COAL, TX_INTR_COAL, DISABLE_COAL, ENABLE_COAL } |
| enum | EXT_PHY_OPTION { SPEED_AUTONEG, SPEED10_HALF, SPEED10_FULL, SPEED100_HALF, SPEED100_FULL } |
| #define AMD8111E_MAX_MTU 9000 |
Definition at line 585 of file amd8111e.h.
| #define AMD8111E_MIN_MTU 60 |
Definition at line 584 of file amd8111e.h.
Definition at line 650 of file amd8111e.h.
Definition at line 590 of file amd8111e.h.
| #define amd8111e_writeq | ( | _UlData, | |
| _memMap | |||
| ) |
| #define AP_VALUE 0x98 /* Auto-poll value register */ |
Definition at line 76 of file amd8111e.h.
| #define ASF_STAT 0x00 /* ASF status register */ |
Definition at line 52 of file amd8111e.h.
| #define AUTONEG_INVALID 0xff |
Definition at line 688 of file amd8111e.h.
| #define AUTOPOLL0 0x88 /* Auto-poll0 register */ |
Definition at line 69 of file amd8111e.h.
| #define AUTOPOLL1 0x8A /* Auto-poll1 register */ |
Definition at line 70 of file amd8111e.h.
| #define AUTOPOLL2 0x8C /* Auto-poll2 register */ |
Definition at line 71 of file amd8111e.h.
| #define AUTOPOLL3 0x8E /* Auto-poll3 register */ |
Definition at line 72 of file amd8111e.h.
| #define AUTOPOLL4 0x90 /* Auto-poll4 register */ |
Definition at line 73 of file amd8111e.h.
| #define AUTOPOLL5 0x92 /* Auto-poll5 register */ |
Definition at line 74 of file amd8111e.h.
| #define CHIPID 0x04 /* Chip ID regsiter */ |
Definition at line 53 of file amd8111e.h.
| #define CMD0 0x48 /* Command0 register */ |
Definition at line 59 of file amd8111e.h.
| #define CMD2 0x50 /* Command2 register */ |
Definition at line 60 of file amd8111e.h.
| #define CMD3 0x54 /* Command3 resiter */ |
Definition at line 61 of file amd8111e.h.
| #define CMD7 0x64 /* Command7 register */ |
Definition at line 62 of file amd8111e.h.
| #define CSTATE 1 |
Definition at line 612 of file amd8111e.h.
| #define CTRL1 0x6C /* Control1 register */ |
Definition at line 64 of file amd8111e.h.
| #define CTRL2 0x70 /* Control2 register */ |
Definition at line 65 of file amd8111e.h.
| #define DEFAULT_IPG 0x60 |
Definition at line 605 of file amd8111e.h.
| #define DELAY_TIMER_CONV |
Definition at line 592 of file amd8111e.h.
| #define DLY_INT_A 0xA8 /* Group A delayed interrupt register */ |
Definition at line 77 of file amd8111e.h.
| #define DLY_INT_B 0xAC /* Group B delayed interrupt register */ |
Definition at line 78 of file amd8111e.h.
| #define DUPLEX_INVALID 0xff |
Definition at line 687 of file amd8111e.h.
| #define FLOW_CONTROL 0xC8 /* Flow control register */ |
Definition at line 80 of file amd8111e.h.
| #define IFS 0x18D /* Inter-frame spacing register */ |
Definition at line 112 of file amd8111e.h.
| #define IFS1 0x18C /* Inter-frame spacing Part1 register */ |
Definition at line 111 of file amd8111e.h.
| #define IFS1_DELTA 36 |
Definition at line 606 of file amd8111e.h.
| #define INT0 0x38 /* Interrupt0 register */ |
Definition at line 57 of file amd8111e.h.
| #define INTEN0 0x40 /* Interrupt0 enable register*/ |
Definition at line 58 of file amd8111e.h.
| #define IPG 0x18E /* Inter-frame gap register */ |
Definition at line 113 of file amd8111e.h.
| #define IPG_CONVERGE_JIFFIES (HZ/2) |
Definition at line 607 of file amd8111e.h.
| #define IPG_STABLE_TIME 5 |
Definition at line 608 of file amd8111e.h.
| #define IPG_STEP 16 |
Definition at line 611 of file amd8111e.h.
| #define LADRF 0x168 /* Logical address filter register */ |
Definition at line 116 of file amd8111e.h.
| #define MAX_EVENT_COUNT 31 |
Definition at line 714 of file amd8111e.h.
| #define MAX_FILTER_SIZE 64 /* Maximum multicast address */ |
Definition at line 583 of file amd8111e.h.
| #define MAX_IPG 255 |
Definition at line 610 of file amd8111e.h.
| #define MAX_TIMEOUT 40 |
Definition at line 713 of file amd8111e.h.
Definition at line 569 of file amd8111e.h.
| #define MIB_ADDR 0x14 /* MIB address register */ |
Definition at line 55 of file amd8111e.h.
| #define MIB_DATA 0x10 /* MIB data register */ |
Definition at line 54 of file amd8111e.h.
| #define MIN_IPG 96 |
Definition at line 609 of file amd8111e.h.
| #define MIN_PKT_LEN 60 |
Definition at line 588 of file amd8111e.h.
| #define NUM_RX_BUFFERS 32 /* Number of receive buffers */ |
Definition at line 572 of file amd8111e.h.
| #define NUM_RX_RING_DR 32 |
Definition at line 578 of file amd8111e.h.
| #define NUM_TX_BUFFERS 32 /* Number of transmit buffers */ |
Definition at line 571 of file amd8111e.h.
| #define NUM_TX_RING_DR 32 |
Definition at line 577 of file amd8111e.h.
| #define OPTION_DYN_IPG_ENABLE 0x0080 |
Definition at line 600 of file amd8111e.h.
| #define OPTION_INTR_COAL_ENABLE 0x0040 |
Definition at line 599 of file amd8111e.h.
| #define OPTION_JUMBO_ENABLE 0x0002 |
Definition at line 594 of file amd8111e.h.
| #define OPTION_MULTICAST_ENABLE 0x0004 |
Definition at line 595 of file amd8111e.h.
| #define OPTION_VLAN_ENABLE 0x0001 |
Definition at line 593 of file amd8111e.h.
| #define OPTION_WAKE_MAGIC_ENABLE 0x0010 |
Definition at line 597 of file amd8111e.h.
| #define OPTION_WAKE_PHY_ENABLE 0x0020 |
Definition at line 598 of file amd8111e.h.
| #define OPTION_WOL_ENABLE 0x0008 |
Definition at line 596 of file amd8111e.h.
| #define PADR 0x160 /* Physical address register */ |
Definition at line 109 of file amd8111e.h.
| #define PCI_DEVICE_ID_AMD8111E_7462 0x7462 |
Definition at line 567 of file amd8111e.h.
| #define PCI_VENDOR_ID_AMD 0x1022 |
Definition at line 566 of file amd8111e.h.
| #define PHY_ACCESS 0xD0 /* PHY access register */ |
Definition at line 81 of file amd8111e.h.
| #define PHY_REG_ADDR_MASK 0x1f |
Definition at line 602 of file amd8111e.h.
| #define PHY_SPEED_10 0x2 |
Definition at line 153 of file amd8111e.h.
| #define PHY_SPEED_100 0x3 |
Definition at line 154 of file amd8111e.h.
| #define PKT_BUFF_SZ 1536 |
Definition at line 587 of file amd8111e.h.
| #define PMAT0 0x190 /* OnNow pattern register0 */ |
Definition at line 92 of file amd8111e.h.
| #define PMAT1 0x194 /* OnNow pattern register1 */ |
Definition at line 93 of file amd8111e.h.
| #define rcv_alignment_errors 0x09 |
Definition at line 519 of file amd8111e.h.
| #define rcv_broadcast_pkts 0x02 |
Definition at line 512 of file amd8111e.h.
| #define rcv_drop_pkts_ring1 0x16 |
Definition at line 532 of file amd8111e.h.
| #define rcv_drop_pkts_ring2 0x17 |
Definition at line 533 of file amd8111e.h.
| #define rcv_drop_pkts_ring3 0x18 |
Definition at line 534 of file amd8111e.h.
| #define rcv_drop_pkts_ring4 0x19 |
Definition at line 535 of file amd8111e.h.
| #define rcv_fcs_errors 0x0A |
Definition at line 520 of file amd8111e.h.
| #define rcv_flow_ctrl 0x0D |
Definition at line 523 of file amd8111e.h.
| #define rcv_fragments 0x06 |
Definition at line 516 of file amd8111e.h.
| #define rcv_good_octets 0x0B |
Definition at line 521 of file amd8111e.h.
| #define rcv_jabbers 0x07 |
Definition at line 517 of file amd8111e.h.
| #define rcv_jumbo_pkts 0x1A |
Definition at line 536 of file amd8111e.h.
| #define rcv_mac_ctrl 0x0C |
Definition at line 522 of file amd8111e.h.
| #define rcv_miss_pkts 0x00 |
Definition at line 510 of file amd8111e.h.
| #define rcv_multicast_pkts 0x03 |
Definition at line 513 of file amd8111e.h.
| #define rcv_octets 0x01 |
Definition at line 511 of file amd8111e.h.
| #define rcv_oversize_pkts 0x05 |
Definition at line 515 of file amd8111e.h.
| #define rcv_pkts_1024to1518_octets 0x13 |
Definition at line 529 of file amd8111e.h.
| #define rcv_pkts_128to255_octets 0x10 |
Definition at line 526 of file amd8111e.h.
| #define rcv_pkts_256to511_octets 0x11 |
Definition at line 527 of file amd8111e.h.
| #define rcv_pkts_512to1023_octets 0x12 |
Definition at line 528 of file amd8111e.h.
| #define rcv_pkts_64_octets 0x0E |
Definition at line 524 of file amd8111e.h.
| #define rcv_pkts_65to127_octets 0x0F |
Definition at line 525 of file amd8111e.h.
| #define RCV_RING_BASE_ADDR0 0x120 /* Transmit ring0 base addr register */ |
Definition at line 90 of file amd8111e.h.
| #define RCV_RING_LEN0 0x150 /* Receive Ring0 length register */ |
Definition at line 102 of file amd8111e.h.
| #define rcv_symbol_errors 0x15 |
Definition at line 531 of file amd8111e.h.
| #define rcv_undersize_pkts 0x04 |
Definition at line 514 of file amd8111e.h.
| #define rcv_unicast_pkts 0x08 |
Definition at line 518 of file amd8111e.h.
| #define rcv_unsupported_opcode 0x14 |
Definition at line 530 of file amd8111e.h.
| #define REPEAT_CNT 10 |
Definition at line 616 of file amd8111e.h.
| #define RESET_RX_FLAGS 0x0000 |
Definition at line 645 of file amd8111e.h.
| #define RX_BUFF_MOD_MASK 31 /* (NUM_RX_BUFFERS -1) */ |
Definition at line 575 of file amd8111e.h.
| #define RX_RING_DR_MOD_MASK 31 /* (NUM_RX_RING_DR -1) */ |
Definition at line 581 of file amd8111e.h.
| #define SOFT_TIMER_FREQ 0xBEBC /* 0.5 sec */ |
Definition at line 591 of file amd8111e.h.
| #define SPEED_INVALID 0xffff |
Definition at line 686 of file amd8111e.h.
| #define SRAM_BOUNDARY 0x17A /* SRAM boundary register */ |
Definition at line 105 of file amd8111e.h.
| #define SRAM_SIZE 0x178 /* SRAM size register */ |
Definition at line 104 of file amd8111e.h.
| #define SSTATE 2 |
Definition at line 613 of file amd8111e.h.
| #define STAT0 0x30 /* Status0 register */ |
Definition at line 56 of file amd8111e.h.
| #define STVAL 0xD8 /* Software timer value register */ |
Definition at line 83 of file amd8111e.h.
| #define TCC_MASK 0x0003 |
Definition at line 647 of file amd8111e.h.
| #define TT_MASK 0x000c |
Definition at line 646 of file amd8111e.h.
| #define TX_BUFF_MOD_MASK 31 /* (NUM_TX_BUFFERS -1) */ |
Definition at line 574 of file amd8111e.h.
| #define TX_RING_DR_MOD_MASK 31 /* (NUM_TX_RING_DR -1) */ |
Definition at line 580 of file amd8111e.h.
| #define xmt_back_pressure 0x2E |
Definition at line 552 of file amd8111e.h.
| #define xmt_broadcast_pkts 0x23 |
Definition at line 541 of file amd8111e.h.
| #define xmt_collisions 0x25 |
Definition at line 543 of file amd8111e.h.
| #define xmt_deferred_transmit 0x29 |
Definition at line 547 of file amd8111e.h.
| #define xmt_excessive_collision 0x2D |
Definition at line 551 of file amd8111e.h.
| #define xmt_excessive_defer 0x2B |
Definition at line 549 of file amd8111e.h.
| #define xmt_flow_ctrl 0x2F |
Definition at line 553 of file amd8111e.h.
| #define xmt_jumbo_pkts 0x37 |
Definition at line 561 of file amd8111e.h.
| #define xmt_late_collision 0x2A |
Definition at line 548 of file amd8111e.h.
| #define xmt_loss_carrier 0x2C |
Definition at line 550 of file amd8111e.h.
| #define xmt_multicast_pkts 0x24 |
Definition at line 542 of file amd8111e.h.
| #define xmt_multiple_collision 0x28 |
Definition at line 546 of file amd8111e.h.
| #define xmt_octets 0x21 |
Definition at line 539 of file amd8111e.h.
| #define xmt_one_collision 0x27 |
Definition at line 545 of file amd8111e.h.
| #define xmt_oversize_pkts 0x36 |
Definition at line 560 of file amd8111e.h.
| #define xmt_packets 0x22 |
Definition at line 540 of file amd8111e.h.
| #define xmt_pkts_1024to1518_octet 0x35 |
Definition at line 559 of file amd8111e.h.
| #define xmt_pkts_128to255_octets 0x32 |
Definition at line 556 of file amd8111e.h.
| #define xmt_pkts_256to511_octets 0x33 |
Definition at line 557 of file amd8111e.h.
| #define xmt_pkts_512to1023_octets 0x34 |
Definition at line 558 of file amd8111e.h.
| #define xmt_pkts_64_octets 0x30 |
Definition at line 554 of file amd8111e.h.
| #define xmt_pkts_65to127_octets 0x31 |
Definition at line 555 of file amd8111e.h.
| #define XMT_RING_BASE_ADDR0 0x100 /* Transmit ring0 base addr register */ |
Definition at line 85 of file amd8111e.h.
| #define XMT_RING_BASE_ADDR1 0x108 /* Transmit ring1 base addr register */ |
Definition at line 86 of file amd8111e.h.
| #define XMT_RING_BASE_ADDR2 0x110 /* Transmit ring2 base addr register */ |
Definition at line 87 of file amd8111e.h.
| #define XMT_RING_BASE_ADDR3 0x118 /* Transmit ring2 base addr register */ |
Definition at line 88 of file amd8111e.h.
| #define XMT_RING_LEN0 0x140 /* Transmit Ring0 length register */ |
Definition at line 97 of file amd8111e.h.
| #define XMT_RING_LEN1 0x144 /* Transmit Ring1 length register */ |
Definition at line 98 of file amd8111e.h.
| #define XMT_RING_LEN2 0x148 /* Transmit Ring2 length register */ |
Definition at line 99 of file amd8111e.h.
| #define XMT_RING_LEN3 0x14C /* Transmit Ring3 length register */ |
Definition at line 100 of file amd8111e.h.
| #define XMT_RING_LIMIT 0x7C /* Transmit ring limit register */ |
Definition at line 67 of file amd8111e.h.
| #define xmt_underrun_pkts 0x20 |
Definition at line 538 of file amd8111e.h.
| #define xmt_unicast_pkts 0x26 |
Definition at line 544 of file amd8111e.h.
| enum AP_VALUE_BITS |
Definition at line 411 of file amd8111e.h.
| enum AUTOPOLL0_BITS |
Definition at line 345 of file amd8111e.h.
| enum AUTOPOLL1_BITS |
Definition at line 354 of file amd8111e.h.
| enum AUTOPOLL2_BITS |
Definition at line 365 of file amd8111e.h.
| enum AUTOPOLL3_BITS |
Definition at line 375 of file amd8111e.h.
| enum AUTOPOLL4_BITS |
Definition at line 386 of file amd8111e.h.
| enum AUTOPOLL5_BITS |
Definition at line 397 of file amd8111e.h.
| enum CMD0_BITS |
| RDMD0 | |
| TDMD3 | |
| TDMD2 | |
| TDMD1 | |
| TDMD0 | |
| UINTCMD | |
| RX_FAST_SPND | |
| TX_FAST_SPND | |
| RX_SPND | |
| TX_SPND | |
| INTREN | |
| RUN | |
| CMD0_CLEAR |
Definition at line 226 of file amd8111e.h.
| enum CMD2_BITS |
| CONDUIT_MODE | |
| RPA | |
| DRCVPA | |
| DRCVBC | |
| PROM | |
| ASTRP_RCV | |
| RCV_DROP0 | |
| EMBA | |
| DXMT2PD | |
| LTINTEN | |
| DXMTFCS | |
| APAD_XMT | |
| DRTY | |
| INLOOP | |
| EXLOOP | |
| REX_RTRY | |
| REX_UFLO | |
| REX_LCOL | |
| CMD2_CLEAR |
Definition at line 247 of file amd8111e.h.
| enum CMD3_BITS |
| ASF_INIT_DONE_ALIAS | |
| JUMBO | |
| VSIZE | |
| VLONLY | |
| VL_TAG_DEL | |
| EN_PMGR | |
| INTLEVEL | |
| FORCE_FULL_DUPLEX | |
| FORCE_LINK_STATUS | |
| APEP | |
| MPPLBA | |
| RESET_PHY_PULSE | |
| RESET_PHY | |
| PHY_RST_POL |
Definition at line 276 of file amd8111e.h.
| enum CMD7_BITS |
Definition at line 300 of file amd8111e.h.
| enum coal_mode |
Definition at line 706 of file amd8111e.h.
| enum coal_type |
Definition at line 697 of file amd8111e.h.
| enum CTRL1_BITS |
| RESET_PHY_WIDTH | |
| XMTSP_MASK | |
| XMTSP_128 | |
| XMTSP_64 | |
| CACHE_ALIGN | |
| BURST_LIMIT_MASK | |
| CTRL1_DEFAULT |
Definition at line 313 of file amd8111e.h.
| enum CTRL2_BITS |
Definition at line 325 of file amd8111e.h.
| enum DLY_INT_A_BITS |
| DLY_INT_A_R3 | |
| DLY_INT_A_R2 | |
| DLY_INT_A_R1 | |
| DLY_INT_A_R0 | |
| DLY_INT_A_T3 | |
| DLY_INT_A_T2 | |
| DLY_INT_A_T1 | |
| DLY_INT_A_T0 | |
| EVENT_COUNT_A | |
| MAX_DELAY_TIME_A |
Definition at line 421 of file amd8111e.h.
| enum DLY_INT_B_BITS |
| DLY_INT_B_R3 | |
| DLY_INT_B_R2 | |
| DLY_INT_B_R1 | |
| DLY_INT_B_R0 | |
| DLY_INT_B_T3 | |
| DLY_INT_B_T2 | |
| DLY_INT_B_T1 | |
| DLY_INT_B_T0 | |
| EVENT_COUNT_B | |
| MAX_DELAY_TIME_B |
Definition at line 437 of file amd8111e.h.
| enum EXT_PHY_OPTION |
Definition at line 799 of file amd8111e.h.
| enum FLOW_CONTROL_BITS |
Definition at line 454 of file amd8111e.h.
| enum INT0_BITS |
| INTR | |
| PCSINT | |
| LCINT | |
| APINT5 | |
| APINT4 | |
| APINT3 | |
| TINT_SUM | |
| APINT2 | |
| APINT1 | |
| APINT0 | |
| MIIPDTINT | |
| MCCINT | |
| MREINT | |
| RINT_SUM | |
| SPNDINT | |
| MPINT | |
| SINT | |
| TINT3 | |
| TINT2 | |
| TINT1 | |
| TINT0 | |
| UINT | |
| STINT | |
| RINT0 |
Definition at line 157 of file amd8111e.h.
| enum INTEN0_BITS |
| LCINTEN | |
| APINT5EN | |
| APINT4EN | |
| APINT3EN | |
| APINT2EN | |
| APINT1EN | |
| APINT0EN | |
| MIIPDTINTEN | |
| MCCIINTEN | |
| MCCINTEN | |
| MREINTEN | |
| SPNDINTEN | |
| MPINTEN | |
| TINTEN3 | |
| SINTEN | |
| TINTEN2 | |
| TINTEN1 | |
| TINTEN0 | |
| STINTEN | |
| RINTEN0 | |
| INTEN0_CLEAR |
Definition at line 195 of file amd8111e.h.
| enum MIB_ADDR_BITS |
Definition at line 127 of file amd8111e.h.
| enum PHY_ACCESS_BITS |
| PHY_CMD_ACTIVE | |
| PHY_WR_CMD | |
| PHY_RD_CMD | |
| PHY_RD_ERR | |
| PHY_PRE_SUP | |
| PHY_ADDR | |
| PHY_REG_ADDR | |
| PHY_DATA |
Definition at line 468 of file amd8111e.h.
| enum PMAT0_BITS |
Definition at line 485 of file amd8111e.h.
| enum PMAT1_BITS |
Definition at line 497 of file amd8111e.h.
| enum RX_FLAG_BITS |
| ERR_BIT | |
| FRAM_BIT | |
| OFLO_BIT | |
| CRC_BIT | |
| PAM_BIT | |
| LAFM_BIT | |
| BAM_BIT | |
| TT_VLAN_TAGGED | |
| TT_PRTY_TAGGED |
Definition at line 632 of file amd8111e.h.
| enum STAT0_BITS |
| PMAT_DET | |
| MP_DET | |
| LC_DET | |
| SPEED_MASK | |
| FULL_DPLX | |
| LINK_STATS | |
| AUTONEG_COMPLETE | |
| MIIPD | |
| RX_SUSPENDED | |
| TX_SUSPENDED | |
| RUNNING |
Definition at line 137 of file amd8111e.h.
| enum STAT_ASF_BITS |
Definition at line 120 of file amd8111e.h.
| enum TX_FLAG_BITS |
Definition at line 619 of file amd8111e.h.
| enum VAL_BITS |
Definition at line 186 of file amd8111e.h.
| enum XMT_RING_LIMIT_BITS |
Definition at line 337 of file amd8111e.h.
1.8.2