#include <linux/types.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/bitops.h>

Macros
#define	AR71XX_APB_BASE 0x18000000

#define	AR71XX_EHCI_BASE 0x1b000000

#define	AR71XX_EHCI_SIZE 0x1000

#define	AR71XX_OHCI_BASE 0x1c000000

#define	AR71XX_OHCI_SIZE 0x1000

#define	AR71XX_SPI_BASE 0x1f000000

#define	AR71XX_SPI_SIZE 0x01000000

#define	AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)

#define	AR71XX_DDR_CTRL_SIZE 0x100

#define	AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)

#define	AR71XX_UART_SIZE 0x100

#define	AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)

#define	AR71XX_USB_CTRL_SIZE 0x100

#define	AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)

#define	AR71XX_GPIO_SIZE 0x100

#define	AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)

#define	AR71XX_PLL_SIZE 0x100

#define	AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)

#define	AR71XX_RESET_SIZE 0x100

#define	AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)

#define	AR7240_USB_CTRL_SIZE 0x100

#define	AR7240_OHCI_BASE 0x1b000000

#define	AR7240_OHCI_SIZE 0x1000

#define	AR724X_EHCI_BASE 0x1b000000

#define	AR724X_EHCI_SIZE 0x1000

#define	AR913X_EHCI_BASE 0x1b000000

#define	AR913X_EHCI_SIZE 0x1000

#define	AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)

#define	AR913X_WMAC_SIZE 0x30000

#define	AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)

#define	AR933X_UART_SIZE 0x14

#define	AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)

#define	AR933X_WMAC_SIZE 0x20000

#define	AR933X_EHCI_BASE 0x1b000000

#define	AR933X_EHCI_SIZE 0x1000

#define	AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)

#define	AR934X_WMAC_SIZE 0x20000

#define	AR934X_EHCI_BASE 0x1b000000

#define	AR934X_EHCI_SIZE 0x200

#define	AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)

#define	AR934X_SRIF_SIZE 0x1000

#define	AR71XX_DDR_REG_PCI_WIN0 0x7c

#define	AR71XX_DDR_REG_PCI_WIN1 0x80

#define	AR71XX_DDR_REG_PCI_WIN2 0x84

#define	AR71XX_DDR_REG_PCI_WIN3 0x88

#define	AR71XX_DDR_REG_PCI_WIN4 0x8c

#define	AR71XX_DDR_REG_PCI_WIN5 0x90

#define	AR71XX_DDR_REG_PCI_WIN6 0x94

#define	AR71XX_DDR_REG_PCI_WIN7 0x98

#define	AR71XX_DDR_REG_FLUSH_GE0 0x9c

#define	AR71XX_DDR_REG_FLUSH_GE1 0xa0

#define	AR71XX_DDR_REG_FLUSH_USB 0xa4

#define	AR71XX_DDR_REG_FLUSH_PCI 0xa8

#define	AR724X_DDR_REG_FLUSH_GE0 0x7c

#define	AR724X_DDR_REG_FLUSH_GE1 0x80

#define	AR724X_DDR_REG_FLUSH_USB 0x84

#define	AR724X_DDR_REG_FLUSH_PCIE 0x88

#define	AR913X_DDR_REG_FLUSH_GE0 0x7c

#define	AR913X_DDR_REG_FLUSH_GE1 0x80

#define	AR913X_DDR_REG_FLUSH_USB 0x84

#define	AR913X_DDR_REG_FLUSH_WMAC 0x88

#define	AR933X_DDR_REG_FLUSH_GE0 0x7c

#define	AR933X_DDR_REG_FLUSH_GE1 0x80

#define	AR933X_DDR_REG_FLUSH_USB 0x84

#define	AR933X_DDR_REG_FLUSH_WMAC 0x88

#define	AR934X_DDR_REG_FLUSH_GE0 0x9c

#define	AR934X_DDR_REG_FLUSH_GE1 0xa0

#define	AR934X_DDR_REG_FLUSH_USB 0xa4

#define	AR934X_DDR_REG_FLUSH_PCIE 0xa8

#define	AR934X_DDR_REG_FLUSH_WMAC 0xac

#define	AR71XX_PLL_REG_CPU_CONFIG 0x00

#define	AR71XX_PLL_REG_SEC_CONFIG 0x04

#define	AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10

#define	AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14

#define	AR71XX_PLL_DIV_SHIFT 3

#define	AR71XX_PLL_DIV_MASK 0x1f

#define	AR71XX_CPU_DIV_SHIFT 16

#define	AR71XX_CPU_DIV_MASK 0x3

#define	AR71XX_DDR_DIV_SHIFT 18

#define	AR71XX_DDR_DIV_MASK 0x3

#define	AR71XX_AHB_DIV_SHIFT 20

#define	AR71XX_AHB_DIV_MASK 0x7

#define	AR724X_PLL_REG_CPU_CONFIG 0x00

#define	AR724X_PLL_REG_PCIE_CONFIG 0x18

#define	AR724X_PLL_DIV_SHIFT 0

#define	AR724X_PLL_DIV_MASK 0x3ff

#define	AR724X_PLL_REF_DIV_SHIFT 10

#define	AR724X_PLL_REF_DIV_MASK 0xf

#define	AR724X_AHB_DIV_SHIFT 19

#define	AR724X_AHB_DIV_MASK 0x1

#define	AR724X_DDR_DIV_SHIFT 22

#define	AR724X_DDR_DIV_MASK 0x3

#define	AR913X_PLL_REG_CPU_CONFIG 0x00

#define	AR913X_PLL_REG_ETH_CONFIG 0x04

#define	AR913X_PLL_REG_ETH0_INT_CLOCK 0x14

#define	AR913X_PLL_REG_ETH1_INT_CLOCK 0x18

#define	AR913X_PLL_DIV_SHIFT 0

#define	AR913X_PLL_DIV_MASK 0x3ff

#define	AR913X_DDR_DIV_SHIFT 22

#define	AR913X_DDR_DIV_MASK 0x3

#define	AR913X_AHB_DIV_SHIFT 19

#define	AR913X_AHB_DIV_MASK 0x1

#define	AR933X_PLL_CPU_CONFIG_REG 0x00

#define	AR933X_PLL_CLOCK_CTRL_REG 0x08

#define	AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10

#define	AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f

#define	AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16

#define	AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f

#define	AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23

#define	AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7

#define	AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)

#define	AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5

#define	AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3

#define	AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10

#define	AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3

#define	AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15

#define	AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7

#define	AR934X_PLL_CPU_CONFIG_REG 0x00

#define	AR934X_PLL_DDR_CONFIG_REG 0x04

#define	AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08

#define	AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0

#define	AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f

#define	AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6

#define	AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f

#define	AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12

#define	AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f

#define	AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19

#define	AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3

#define	AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0

#define	AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff

#define	AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10

#define	AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f

#define	AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16

#define	AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f

#define	AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23

#define	AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7

#define	AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)

#define	AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)

#define	AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)

#define	AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5

#define	AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f

#define	AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10

#define	AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f

#define	AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15

#define	AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f

#define	AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)

#define	AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)

#define	AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)

#define	AR71XX_USB_CTRL_REG_FLADJ 0x00

#define	AR71XX_USB_CTRL_REG_CONFIG 0x04

#define	AR71XX_RESET_REG_TIMER 0x00

#define	AR71XX_RESET_REG_TIMER_RELOAD 0x04

#define	AR71XX_RESET_REG_WDOG_CTRL 0x08

#define	AR71XX_RESET_REG_WDOG 0x0c

#define	AR71XX_RESET_REG_MISC_INT_STATUS 0x10

#define	AR71XX_RESET_REG_MISC_INT_ENABLE 0x14

#define	AR71XX_RESET_REG_PCI_INT_STATUS 0x18

#define	AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c

#define	AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20

#define	AR71XX_RESET_REG_RESET_MODULE 0x24

#define	AR71XX_RESET_REG_PERFC_CTRL 0x2c

#define	AR71XX_RESET_REG_PERFC0 0x30

#define	AR71XX_RESET_REG_PERFC1 0x34

#define	AR71XX_RESET_REG_REV_ID 0x90

#define	AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18

#define	AR913X_RESET_REG_RESET_MODULE 0x1c

#define	AR913X_RESET_REG_PERF_CTRL 0x20

#define	AR913X_RESET_REG_PERFC0 0x24

#define	AR913X_RESET_REG_PERFC1 0x28

#define	AR724X_RESET_REG_RESET_MODULE 0x1c

#define	AR933X_RESET_REG_RESET_MODULE 0x1c

#define	AR933X_RESET_REG_BOOTSTRAP 0xac

#define	AR934X_RESET_REG_RESET_MODULE 0x1c

#define	AR934X_RESET_REG_BOOTSTRAP 0xb0

#define	AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac

#define	MISC_INT_ETHSW BIT(12)

#define	MISC_INT_TIMER4 BIT(10)

#define	MISC_INT_TIMER3 BIT(9)

#define	MISC_INT_TIMER2 BIT(8)

#define	MISC_INT_DMA BIT(7)

#define	MISC_INT_OHCI BIT(6)

#define	MISC_INT_PERFC BIT(5)

#define	MISC_INT_WDOG BIT(4)

#define	MISC_INT_UART BIT(3)

#define	MISC_INT_GPIO BIT(2)

#define	MISC_INT_ERROR BIT(1)

#define	MISC_INT_TIMER BIT(0)

#define	AR71XX_RESET_EXTERNAL BIT(28)

#define	AR71XX_RESET_FULL_CHIP BIT(24)

#define	AR71XX_RESET_CPU_NMI BIT(21)

#define	AR71XX_RESET_CPU_COLD BIT(20)

#define	AR71XX_RESET_DMA BIT(19)

#define	AR71XX_RESET_SLIC BIT(18)

#define	AR71XX_RESET_STEREO BIT(17)

#define	AR71XX_RESET_DDR BIT(16)

#define	AR71XX_RESET_GE1_MAC BIT(13)

#define	AR71XX_RESET_GE1_PHY BIT(12)

#define	AR71XX_RESET_USBSUS_OVERRIDE BIT(10)

#define	AR71XX_RESET_GE0_MAC BIT(9)

#define	AR71XX_RESET_GE0_PHY BIT(8)

#define	AR71XX_RESET_USB_OHCI_DLL BIT(6)

#define	AR71XX_RESET_USB_HOST BIT(5)

#define	AR71XX_RESET_USB_PHY BIT(4)

#define	AR71XX_RESET_PCI_BUS BIT(1)

#define	AR71XX_RESET_PCI_CORE BIT(0)

#define	AR7240_RESET_USB_HOST BIT(5)

#define	AR7240_RESET_OHCI_DLL BIT(3)

#define	AR724X_RESET_GE1_MDIO BIT(23)

#define	AR724X_RESET_GE0_MDIO BIT(22)

#define	AR724X_RESET_PCIE_PHY_SERIAL BIT(10)

#define	AR724X_RESET_PCIE_PHY BIT(7)

#define	AR724X_RESET_PCIE BIT(6)

#define	AR724X_RESET_USB_HOST BIT(5)

#define	AR724X_RESET_USB_PHY BIT(4)

#define	AR724X_RESET_USBSUS_OVERRIDE BIT(3)

#define	AR913X_RESET_AMBA2WMAC BIT(22)

#define	AR913X_RESET_USBSUS_OVERRIDE BIT(10)

#define	AR913X_RESET_USB_HOST BIT(5)

#define	AR913X_RESET_USB_PHY BIT(4)

#define	AR933X_RESET_WMAC BIT(11)

#define	AR933X_RESET_USB_HOST BIT(5)

#define	AR933X_RESET_USB_PHY BIT(4)

#define	AR933X_RESET_USBSUS_OVERRIDE BIT(3)

#define	AR934X_RESET_USB_PHY_ANALOG BIT(11)

#define	AR934X_RESET_USB_HOST BIT(5)

#define	AR934X_RESET_USB_PHY BIT(4)

#define	AR934X_RESET_USBSUS_OVERRIDE BIT(3)

#define	AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)

#define	AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)

#define	AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)

#define	AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)

#define	AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)

#define	AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)

#define	AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)

#define	AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)

#define	AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)

#define	AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)

#define	AR934X_BOOTSTRAP_PCIE_RC BIT(6)

#define	AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)

#define	AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)

#define	AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)

#define	AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)

#define	AR934X_BOOTSTRAP_DDR1 BIT(0)

#define	AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)

#define	AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)

#define	AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)

#define	AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)

#define	AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)

#define	AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)

#define	AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)

#define	AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)

#define	AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)

#define	AR934X_PCIE_WMAC_INT_WMAC_ALL

#define	AR934X_PCIE_WMAC_INT_PCIE_ALL

#define	REV_ID_MAJOR_MASK 0xfff0

#define	REV_ID_MAJOR_AR71XX 0x00a0

#define	REV_ID_MAJOR_AR913X 0x00b0

#define	REV_ID_MAJOR_AR7240 0x00c0

#define	REV_ID_MAJOR_AR7241 0x0100

#define	REV_ID_MAJOR_AR7242 0x1100

#define	REV_ID_MAJOR_AR9330 0x0110

#define	REV_ID_MAJOR_AR9331 0x1110

#define	REV_ID_MAJOR_AR9341 0x0120

#define	REV_ID_MAJOR_AR9342 0x1120

#define	REV_ID_MAJOR_AR9344 0x2120

#define	AR71XX_REV_ID_MINOR_MASK 0x3

#define	AR71XX_REV_ID_MINOR_AR7130 0x0

#define	AR71XX_REV_ID_MINOR_AR7141 0x1

#define	AR71XX_REV_ID_MINOR_AR7161 0x2

#define	AR71XX_REV_ID_REVISION_MASK 0x3

#define	AR71XX_REV_ID_REVISION_SHIFT 2

#define	AR913X_REV_ID_MINOR_MASK 0x3

#define	AR913X_REV_ID_MINOR_AR9130 0x0

#define	AR913X_REV_ID_MINOR_AR9132 0x1

#define	AR913X_REV_ID_REVISION_MASK 0x3

#define	AR913X_REV_ID_REVISION_SHIFT 2

#define	AR933X_REV_ID_REVISION_MASK 0x3

#define	AR724X_REV_ID_REVISION_MASK 0x3

#define	AR934X_REV_ID_REVISION_MASK 0xf

#define	AR71XX_SPI_REG_FS 0x00 /* Function Select */

#define	AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */

#define	AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */

#define	AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */

#define	AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */

#define	AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */

#define	AR71XX_SPI_CTRL_DIV_MASK 0x3f

#define	AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */

#define	AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */

#define	AR71XX_SPI_IOC_CS(n) BIT(16 + (n))

#define	AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)

#define	AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1)

#define	AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2)

#define	AR71XX_SPI_IOC_CS_ALL

#define	AR71XX_GPIO_REG_OE 0x00

#define	AR71XX_GPIO_REG_IN 0x04

#define	AR71XX_GPIO_REG_OUT 0x08

#define	AR71XX_GPIO_REG_SET 0x0c

#define	AR71XX_GPIO_REG_CLEAR 0x10

#define	AR71XX_GPIO_REG_INT_MODE 0x14

#define	AR71XX_GPIO_REG_INT_TYPE 0x18

#define	AR71XX_GPIO_REG_INT_POLARITY 0x1c

#define	AR71XX_GPIO_REG_INT_PENDING 0x20

#define	AR71XX_GPIO_REG_INT_ENABLE 0x24

#define	AR71XX_GPIO_REG_FUNC 0x28

#define	AR71XX_GPIO_COUNT 16

#define	AR7240_GPIO_COUNT 18

#define	AR7241_GPIO_COUNT 20

#define	AR913X_GPIO_COUNT 22

#define	AR933X_GPIO_COUNT 30

#define	AR934X_GPIO_COUNT 23

#define	AR934X_SRIF_CPU_DPLL1_REG 0x1c0

#define	AR934X_SRIF_CPU_DPLL2_REG 0x1c4

#define	AR934X_SRIF_CPU_DPLL3_REG 0x1c8

#define	AR934X_SRIF_DDR_DPLL1_REG 0x240

#define	AR934X_SRIF_DDR_DPLL2_REG 0x244

#define	AR934X_SRIF_DDR_DPLL3_REG 0x248

#define	AR934X_SRIF_DPLL1_REFDIV_SHIFT 27

#define	AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f

#define	AR934X_SRIF_DPLL1_NINT_SHIFT 18

#define	AR934X_SRIF_DPLL1_NINT_MASK 0x1ff

#define	AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff

#define	AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30)

#define	AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13

#define	AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7

Macro Definition Documentation

#define AR71XX_AHB_DIV_MASK 0x7

Definition at line 123 of file ar71xx_regs.h.

#define AR71XX_AHB_DIV_SHIFT 20

Definition at line 122 of file ar71xx_regs.h.

#define AR71XX_APB_BASE 0x18000000

Definition at line 23 of file ar71xx_regs.h.

#define AR71XX_CPU_DIV_MASK 0x3

Definition at line 119 of file ar71xx_regs.h.

#define AR71XX_CPU_DIV_SHIFT 16

Definition at line 118 of file ar71xx_regs.h.

#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)

Definition at line 31 of file ar71xx_regs.h.

#define AR71XX_DDR_CTRL_SIZE 0x100

Definition at line 32 of file ar71xx_regs.h.

#define AR71XX_DDR_DIV_MASK 0x3

Definition at line 121 of file ar71xx_regs.h.

#define AR71XX_DDR_DIV_SHIFT 18

Definition at line 120 of file ar71xx_regs.h.

#define AR71XX_DDR_REG_FLUSH_GE0 0x9c

Definition at line 82 of file ar71xx_regs.h.

#define AR71XX_DDR_REG_FLUSH_GE1 0xa0

Definition at line 83 of file ar71xx_regs.h.

#define AR71XX_DDR_REG_FLUSH_PCI 0xa8

Definition at line 85 of file ar71xx_regs.h.

#define AR71XX_DDR_REG_FLUSH_USB 0xa4

Definition at line 84 of file ar71xx_regs.h.

#define AR71XX_DDR_REG_PCI_WIN0 0x7c

Definition at line 74 of file ar71xx_regs.h.

#define AR71XX_DDR_REG_PCI_WIN1 0x80

Definition at line 75 of file ar71xx_regs.h.

#define AR71XX_DDR_REG_PCI_WIN2 0x84

Definition at line 76 of file ar71xx_regs.h.

#define AR71XX_DDR_REG_PCI_WIN3 0x88

Definition at line 77 of file ar71xx_regs.h.

#define AR71XX_DDR_REG_PCI_WIN4 0x8c

Definition at line 78 of file ar71xx_regs.h.

#define AR71XX_DDR_REG_PCI_WIN5 0x90

Definition at line 79 of file ar71xx_regs.h.

#define AR71XX_DDR_REG_PCI_WIN6 0x94

Definition at line 80 of file ar71xx_regs.h.

#define AR71XX_DDR_REG_PCI_WIN7 0x98

Definition at line 81 of file ar71xx_regs.h.

#define AR71XX_EHCI_BASE 0x1b000000

Definition at line 24 of file ar71xx_regs.h.

#define AR71XX_EHCI_SIZE 0x1000

Definition at line 25 of file ar71xx_regs.h.

#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)

Definition at line 37 of file ar71xx_regs.h.

#define AR71XX_GPIO_COUNT 16

Definition at line 404 of file ar71xx_regs.h.

#define AR71XX_GPIO_REG_CLEAR 0x10

Definition at line 396 of file ar71xx_regs.h.

#define AR71XX_GPIO_REG_FUNC 0x28

Definition at line 402 of file ar71xx_regs.h.

#define AR71XX_GPIO_REG_IN 0x04

Definition at line 393 of file ar71xx_regs.h.

#define AR71XX_GPIO_REG_INT_ENABLE 0x24

Definition at line 401 of file ar71xx_regs.h.

#define AR71XX_GPIO_REG_INT_MODE 0x14

Definition at line 397 of file ar71xx_regs.h.

#define AR71XX_GPIO_REG_INT_PENDING 0x20

Definition at line 400 of file ar71xx_regs.h.

#define AR71XX_GPIO_REG_INT_POLARITY 0x1c

Definition at line 399 of file ar71xx_regs.h.

#define AR71XX_GPIO_REG_INT_TYPE 0x18

Definition at line 398 of file ar71xx_regs.h.

#define AR71XX_GPIO_REG_OE 0x00

Definition at line 392 of file ar71xx_regs.h.

#define AR71XX_GPIO_REG_OUT 0x08

Definition at line 394 of file ar71xx_regs.h.

#define AR71XX_GPIO_REG_SET 0x0c

Definition at line 395 of file ar71xx_regs.h.

#define AR71XX_GPIO_SIZE 0x100

Definition at line 38 of file ar71xx_regs.h.

#define AR71XX_OHCI_BASE 0x1c000000

Definition at line 26 of file ar71xx_regs.h.

#define AR71XX_OHCI_SIZE 0x1000

Definition at line 27 of file ar71xx_regs.h.

#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)

Definition at line 39 of file ar71xx_regs.h.

#define AR71XX_PLL_DIV_MASK 0x1f

Definition at line 117 of file ar71xx_regs.h.

#define AR71XX_PLL_DIV_SHIFT 3

Definition at line 116 of file ar71xx_regs.h.

#define AR71XX_PLL_REG_CPU_CONFIG 0x00

Definition at line 111 of file ar71xx_regs.h.

#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10

Definition at line 113 of file ar71xx_regs.h.

#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14

Definition at line 114 of file ar71xx_regs.h.

#define AR71XX_PLL_REG_SEC_CONFIG 0x04

Definition at line 112 of file ar71xx_regs.h.

#define AR71XX_PLL_SIZE 0x100

Definition at line 40 of file ar71xx_regs.h.

#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)

Definition at line 41 of file ar71xx_regs.h.

#define AR71XX_RESET_CPU_COLD BIT(20)

Definition at line 257 of file ar71xx_regs.h.

#define AR71XX_RESET_CPU_NMI BIT(21)

Definition at line 256 of file ar71xx_regs.h.

#define AR71XX_RESET_DDR BIT(16)

Definition at line 261 of file ar71xx_regs.h.

#define AR71XX_RESET_DMA BIT(19)

Definition at line 258 of file ar71xx_regs.h.

#define AR71XX_RESET_EXTERNAL BIT(28)

Definition at line 254 of file ar71xx_regs.h.

#define AR71XX_RESET_FULL_CHIP BIT(24)

Definition at line 255 of file ar71xx_regs.h.

#define AR71XX_RESET_GE0_MAC BIT(9)

Definition at line 265 of file ar71xx_regs.h.

#define AR71XX_RESET_GE0_PHY BIT(8)

Definition at line 266 of file ar71xx_regs.h.

#define AR71XX_RESET_GE1_MAC BIT(13)

Definition at line 262 of file ar71xx_regs.h.

#define AR71XX_RESET_GE1_PHY BIT(12)

Definition at line 263 of file ar71xx_regs.h.

#define AR71XX_RESET_PCI_BUS BIT(1)

Definition at line 270 of file ar71xx_regs.h.

#define AR71XX_RESET_PCI_CORE BIT(0)

Definition at line 271 of file ar71xx_regs.h.

#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20

Definition at line 219 of file ar71xx_regs.h.

#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14

Definition at line 216 of file ar71xx_regs.h.

#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10

Definition at line 215 of file ar71xx_regs.h.

#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c

Definition at line 218 of file ar71xx_regs.h.

#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18

Definition at line 217 of file ar71xx_regs.h.

#define AR71XX_RESET_REG_PERFC0 0x30

Definition at line 222 of file ar71xx_regs.h.

#define AR71XX_RESET_REG_PERFC1 0x34

Definition at line 223 of file ar71xx_regs.h.

#define AR71XX_RESET_REG_PERFC_CTRL 0x2c

Definition at line 221 of file ar71xx_regs.h.

#define AR71XX_RESET_REG_RESET_MODULE 0x24

Definition at line 220 of file ar71xx_regs.h.

#define AR71XX_RESET_REG_REV_ID 0x90

Definition at line 224 of file ar71xx_regs.h.

#define AR71XX_RESET_REG_TIMER 0x00

Definition at line 211 of file ar71xx_regs.h.

#define AR71XX_RESET_REG_TIMER_RELOAD 0x04

Definition at line 212 of file ar71xx_regs.h.

#define AR71XX_RESET_REG_WDOG 0x0c

Definition at line 214 of file ar71xx_regs.h.

#define AR71XX_RESET_REG_WDOG_CTRL 0x08

Definition at line 213 of file ar71xx_regs.h.

#define AR71XX_RESET_SIZE 0x100

Definition at line 42 of file ar71xx_regs.h.

#define AR71XX_RESET_SLIC BIT(18)

Definition at line 259 of file ar71xx_regs.h.

#define AR71XX_RESET_STEREO BIT(17)

Definition at line 260 of file ar71xx_regs.h.

#define AR71XX_RESET_USB_HOST BIT(5)

Definition at line 268 of file ar71xx_regs.h.

#define AR71XX_RESET_USB_OHCI_DLL BIT(6)

Definition at line 267 of file ar71xx_regs.h.

#define AR71XX_RESET_USB_PHY BIT(4)

Definition at line 269 of file ar71xx_regs.h.

#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10)

Definition at line 264 of file ar71xx_regs.h.

#define AR71XX_REV_ID_MINOR_AR7130 0x0

Definition at line 349 of file ar71xx_regs.h.

#define AR71XX_REV_ID_MINOR_AR7141 0x1

Definition at line 350 of file ar71xx_regs.h.

#define AR71XX_REV_ID_MINOR_AR7161 0x2

Definition at line 351 of file ar71xx_regs.h.

#define AR71XX_REV_ID_MINOR_MASK 0x3

Definition at line 348 of file ar71xx_regs.h.

#define AR71XX_REV_ID_REVISION_MASK 0x3

Definition at line 352 of file ar71xx_regs.h.

#define AR71XX_REV_ID_REVISION_SHIFT 2

Definition at line 353 of file ar71xx_regs.h.

#define AR71XX_SPI_BASE 0x1f000000

Definition at line 28 of file ar71xx_regs.h.

#define AR71XX_SPI_CTRL_DIV_MASK 0x3f

Definition at line 378 of file ar71xx_regs.h.

#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */

Definition at line 377 of file ar71xx_regs.h.

#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */

Definition at line 375 of file ar71xx_regs.h.

#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */

Definition at line 381 of file ar71xx_regs.h.

#define AR71XX_SPI_IOC_CS ( n ) BIT(16 + (n))

Definition at line 382 of file ar71xx_regs.h.

#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)

Definition at line 383 of file ar71xx_regs.h.

#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1)

Definition at line 384 of file ar71xx_regs.h.

#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2)

Definition at line 385 of file ar71xx_regs.h.

#define AR71XX_SPI_IOC_CS_ALL

Value:

(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \

AR71XX_SPI_IOC_CS2)

Definition at line 386 of file ar71xx_regs.h.

#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */

Definition at line 380 of file ar71xx_regs.h.

#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */

Definition at line 371 of file ar71xx_regs.h.

#define AR71XX_SPI_REG_FS 0x00 /* Function Select */

Definition at line 370 of file ar71xx_regs.h.

#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */

Definition at line 372 of file ar71xx_regs.h.

#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */

Definition at line 373 of file ar71xx_regs.h.

#define AR71XX_SPI_SIZE 0x01000000

Definition at line 29 of file ar71xx_regs.h.

#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)

Definition at line 33 of file ar71xx_regs.h.

#define AR71XX_UART_SIZE 0x100

Definition at line 34 of file ar71xx_regs.h.

#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)

Definition at line 35 of file ar71xx_regs.h.

#define AR71XX_USB_CTRL_REG_CONFIG 0x04

Definition at line 206 of file ar71xx_regs.h.

#define AR71XX_USB_CTRL_REG_FLADJ 0x00

Definition at line 205 of file ar71xx_regs.h.

#define AR71XX_USB_CTRL_SIZE 0x100

Definition at line 36 of file ar71xx_regs.h.

#define AR7240_GPIO_COUNT 18

Definition at line 405 of file ar71xx_regs.h.

#define AR7240_OHCI_BASE 0x1b000000

Definition at line 46 of file ar71xx_regs.h.

#define AR7240_OHCI_SIZE 0x1000

Definition at line 47 of file ar71xx_regs.h.

#define AR7240_RESET_OHCI_DLL BIT(3)

Definition at line 274 of file ar71xx_regs.h.

#define AR7240_RESET_USB_HOST BIT(5)

Definition at line 273 of file ar71xx_regs.h.

#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)

Definition at line 44 of file ar71xx_regs.h.

#define AR7240_USB_CTRL_SIZE 0x100

Definition at line 45 of file ar71xx_regs.h.

#define AR7241_GPIO_COUNT 20

Definition at line 406 of file ar71xx_regs.h.

#define AR724X_AHB_DIV_MASK 0x1

Definition at line 133 of file ar71xx_regs.h.

#define AR724X_AHB_DIV_SHIFT 19

Definition at line 132 of file ar71xx_regs.h.

#define AR724X_DDR_DIV_MASK 0x3

Definition at line 135 of file ar71xx_regs.h.

#define AR724X_DDR_DIV_SHIFT 22

Definition at line 134 of file ar71xx_regs.h.

#define AR724X_DDR_REG_FLUSH_GE0 0x7c

Definition at line 87 of file ar71xx_regs.h.

#define AR724X_DDR_REG_FLUSH_GE1 0x80

Definition at line 88 of file ar71xx_regs.h.

#define AR724X_DDR_REG_FLUSH_PCIE 0x88

Definition at line 90 of file ar71xx_regs.h.

#define AR724X_DDR_REG_FLUSH_USB 0x84

Definition at line 89 of file ar71xx_regs.h.

#define AR724X_EHCI_BASE 0x1b000000

Definition at line 49 of file ar71xx_regs.h.

#define AR724X_EHCI_SIZE 0x1000

Definition at line 50 of file ar71xx_regs.h.

#define AR724X_PLL_DIV_MASK 0x3ff

Definition at line 129 of file ar71xx_regs.h.

#define AR724X_PLL_DIV_SHIFT 0

Definition at line 128 of file ar71xx_regs.h.

#define AR724X_PLL_REF_DIV_MASK 0xf

Definition at line 131 of file ar71xx_regs.h.

#define AR724X_PLL_REF_DIV_SHIFT 10

Definition at line 130 of file ar71xx_regs.h.

#define AR724X_PLL_REG_CPU_CONFIG 0x00

Definition at line 125 of file ar71xx_regs.h.

#define AR724X_PLL_REG_PCIE_CONFIG 0x18

Definition at line 126 of file ar71xx_regs.h.

#define AR724X_RESET_GE0_MDIO BIT(22)

Definition at line 277 of file ar71xx_regs.h.

#define AR724X_RESET_GE1_MDIO BIT(23)

Definition at line 276 of file ar71xx_regs.h.

#define AR724X_RESET_PCIE BIT(6)

Definition at line 280 of file ar71xx_regs.h.

#define AR724X_RESET_PCIE_PHY BIT(7)

Definition at line 279 of file ar71xx_regs.h.

#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)

Definition at line 278 of file ar71xx_regs.h.

#define AR724X_RESET_REG_RESET_MODULE 0x1c

Definition at line 232 of file ar71xx_regs.h.

#define AR724X_RESET_USB_HOST BIT(5)

Definition at line 281 of file ar71xx_regs.h.

#define AR724X_RESET_USB_PHY BIT(4)

Definition at line 282 of file ar71xx_regs.h.

#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)

Definition at line 283 of file ar71xx_regs.h.

#define AR724X_REV_ID_REVISION_MASK 0x3

Definition at line 363 of file ar71xx_regs.h.

#define AR913X_AHB_DIV_MASK 0x1

Definition at line 147 of file ar71xx_regs.h.

#define AR913X_AHB_DIV_SHIFT 19

Definition at line 146 of file ar71xx_regs.h.

#define AR913X_DDR_DIV_MASK 0x3

Definition at line 145 of file ar71xx_regs.h.

#define AR913X_DDR_DIV_SHIFT 22

Definition at line 144 of file ar71xx_regs.h.

#define AR913X_DDR_REG_FLUSH_GE0 0x7c

Definition at line 92 of file ar71xx_regs.h.

#define AR913X_DDR_REG_FLUSH_GE1 0x80

Definition at line 93 of file ar71xx_regs.h.

#define AR913X_DDR_REG_FLUSH_USB 0x84

Definition at line 94 of file ar71xx_regs.h.

#define AR913X_DDR_REG_FLUSH_WMAC 0x88

Definition at line 95 of file ar71xx_regs.h.

#define AR913X_EHCI_BASE 0x1b000000

Definition at line 52 of file ar71xx_regs.h.

#define AR913X_EHCI_SIZE 0x1000

Definition at line 53 of file ar71xx_regs.h.

#define AR913X_GPIO_COUNT 22

Definition at line 407 of file ar71xx_regs.h.

#define AR913X_PLL_DIV_MASK 0x3ff

Definition at line 143 of file ar71xx_regs.h.

#define AR913X_PLL_DIV_SHIFT 0

Definition at line 142 of file ar71xx_regs.h.

#define AR913X_PLL_REG_CPU_CONFIG 0x00

Definition at line 137 of file ar71xx_regs.h.

#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14

Definition at line 139 of file ar71xx_regs.h.

#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18

Definition at line 140 of file ar71xx_regs.h.

#define AR913X_PLL_REG_ETH_CONFIG 0x04

Definition at line 138 of file ar71xx_regs.h.

#define AR913X_RESET_AMBA2WMAC BIT(22)

Definition at line 285 of file ar71xx_regs.h.

#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18

Definition at line 226 of file ar71xx_regs.h.

#define AR913X_RESET_REG_PERF_CTRL 0x20

Definition at line 228 of file ar71xx_regs.h.

#define AR913X_RESET_REG_PERFC0 0x24

Definition at line 229 of file ar71xx_regs.h.

#define AR913X_RESET_REG_PERFC1 0x28

Definition at line 230 of file ar71xx_regs.h.

#define AR913X_RESET_REG_RESET_MODULE 0x1c

Definition at line 227 of file ar71xx_regs.h.

#define AR913X_RESET_USB_HOST BIT(5)

Definition at line 287 of file ar71xx_regs.h.

#define AR913X_RESET_USB_PHY BIT(4)

Definition at line 288 of file ar71xx_regs.h.

#define AR913X_RESET_USBSUS_OVERRIDE BIT(10)

Definition at line 286 of file ar71xx_regs.h.

#define AR913X_REV_ID_MINOR_AR9130 0x0

Definition at line 356 of file ar71xx_regs.h.

#define AR913X_REV_ID_MINOR_AR9132 0x1

Definition at line 357 of file ar71xx_regs.h.

#define AR913X_REV_ID_MINOR_MASK 0x3

Definition at line 355 of file ar71xx_regs.h.

#define AR913X_REV_ID_REVISION_MASK 0x3

Definition at line 358 of file ar71xx_regs.h.

#define AR913X_REV_ID_REVISION_SHIFT 2

Definition at line 359 of file ar71xx_regs.h.

#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)

Definition at line 54 of file ar71xx_regs.h.

#define AR913X_WMAC_SIZE 0x30000

Definition at line 55 of file ar71xx_regs.h.

#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)

Definition at line 300 of file ar71xx_regs.h.

#define AR933X_DDR_REG_FLUSH_GE0 0x7c

Definition at line 97 of file ar71xx_regs.h.

#define AR933X_DDR_REG_FLUSH_GE1 0x80

Definition at line 98 of file ar71xx_regs.h.

#define AR933X_DDR_REG_FLUSH_USB 0x84

Definition at line 99 of file ar71xx_regs.h.

#define AR933X_DDR_REG_FLUSH_WMAC 0x88

Definition at line 100 of file ar71xx_regs.h.

#define AR933X_EHCI_BASE 0x1b000000

Definition at line 61 of file ar71xx_regs.h.

#define AR933X_EHCI_SIZE 0x1000

Definition at line 62 of file ar71xx_regs.h.

#define AR933X_GPIO_COUNT 30

Definition at line 408 of file ar71xx_regs.h.

#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7

Definition at line 165 of file ar71xx_regs.h.

#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15

Definition at line 164 of file ar71xx_regs.h.

#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)

Definition at line 159 of file ar71xx_regs.h.

#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3

Definition at line 161 of file ar71xx_regs.h.

#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5

Definition at line 160 of file ar71xx_regs.h.

#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3

Definition at line 163 of file ar71xx_regs.h.

#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10

Definition at line 162 of file ar71xx_regs.h.

#define AR933X_PLL_CLOCK_CTRL_REG 0x08

Definition at line 150 of file ar71xx_regs.h.

#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f

Definition at line 153 of file ar71xx_regs.h.

#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10

Definition at line 152 of file ar71xx_regs.h.

#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7

Definition at line 157 of file ar71xx_regs.h.

#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23

Definition at line 156 of file ar71xx_regs.h.

#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f

Definition at line 155 of file ar71xx_regs.h.

#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16

Definition at line 154 of file ar71xx_regs.h.

#define AR933X_PLL_CPU_CONFIG_REG 0x00

Definition at line 149 of file ar71xx_regs.h.

#define AR933X_RESET_REG_BOOTSTRAP 0xac

Definition at line 235 of file ar71xx_regs.h.

#define AR933X_RESET_REG_RESET_MODULE 0x1c

Definition at line 234 of file ar71xx_regs.h.

#define AR933X_RESET_USB_HOST BIT(5)

Definition at line 291 of file ar71xx_regs.h.

#define AR933X_RESET_USB_PHY BIT(4)

Definition at line 292 of file ar71xx_regs.h.

#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)

Definition at line 293 of file ar71xx_regs.h.

#define AR933X_RESET_WMAC BIT(11)

Definition at line 290 of file ar71xx_regs.h.

#define AR933X_REV_ID_REVISION_MASK 0x3

Definition at line 361 of file ar71xx_regs.h.

#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)

Definition at line 57 of file ar71xx_regs.h.

#define AR933X_UART_SIZE 0x14

Definition at line 58 of file ar71xx_regs.h.

#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)

Definition at line 59 of file ar71xx_regs.h.

#define AR933X_WMAC_SIZE 0x20000

Definition at line 60 of file ar71xx_regs.h.

#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)

Definition at line 314 of file ar71xx_regs.h.

#define AR934X_BOOTSTRAP_DDR1 BIT(0)

Definition at line 316 of file ar71xx_regs.h.

#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)

Definition at line 312 of file ar71xx_regs.h.

#define AR934X_BOOTSTRAP_PCIE_RC BIT(6)

Definition at line 311 of file ar71xx_regs.h.

#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)

Definition at line 313 of file ar71xx_regs.h.

#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)

Definition at line 315 of file ar71xx_regs.h.

#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)

Definition at line 309 of file ar71xx_regs.h.

#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)

Definition at line 308 of file ar71xx_regs.h.

#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)

Definition at line 307 of file ar71xx_regs.h.

#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)

Definition at line 306 of file ar71xx_regs.h.

#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)

Definition at line 305 of file ar71xx_regs.h.

#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)

Definition at line 304 of file ar71xx_regs.h.

#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)

Definition at line 303 of file ar71xx_regs.h.

#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)

Definition at line 302 of file ar71xx_regs.h.

#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)

Definition at line 310 of file ar71xx_regs.h.

#define AR934X_DDR_REG_FLUSH_GE0 0x9c

Definition at line 102 of file ar71xx_regs.h.

#define AR934X_DDR_REG_FLUSH_GE1 0xa0

Definition at line 103 of file ar71xx_regs.h.

#define AR934X_DDR_REG_FLUSH_PCIE 0xa8

Definition at line 105 of file ar71xx_regs.h.

#define AR934X_DDR_REG_FLUSH_USB 0xa4

Definition at line 104 of file ar71xx_regs.h.

#define AR934X_DDR_REG_FLUSH_WMAC 0xac

Definition at line 106 of file ar71xx_regs.h.

#define AR934X_EHCI_BASE 0x1b000000

Definition at line 66 of file ar71xx_regs.h.

#define AR934X_EHCI_SIZE 0x200

Definition at line 67 of file ar71xx_regs.h.

#define AR934X_GPIO_COUNT 23

Definition at line 409 of file ar71xx_regs.h.

#define AR934X_PCIE_WMAC_INT_PCIE_ALL

Value:

(AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
     AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
     AR934X_PCIE_WMAC_INT_PCIE_RC3)

Definition at line 331 of file ar71xx_regs.h.

#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)

Definition at line 322 of file ar71xx_regs.h.

#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)

Definition at line 323 of file ar71xx_regs.h.

#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)

Definition at line 324 of file ar71xx_regs.h.

#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)

Definition at line 325 of file ar71xx_regs.h.

#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)

Definition at line 326 of file ar71xx_regs.h.

#define AR934X_PCIE_WMAC_INT_WMAC_ALL

Value:

(AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \

AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)

Definition at line 327 of file ar71xx_regs.h.

#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)

Definition at line 318 of file ar71xx_regs.h.

#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)

Definition at line 321 of file ar71xx_regs.h.

#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)

Definition at line 320 of file ar71xx_regs.h.

#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)

Definition at line 319 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f

Definition at line 172 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0

Definition at line 171 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f

Definition at line 174 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6

Definition at line 173 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3

Definition at line 178 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19

Definition at line 177 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f

Definition at line 176 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12

Definition at line 175 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_CONFIG_REG 0x00

Definition at line 167 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)

Definition at line 191 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f

Definition at line 197 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15

Definition at line 196 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)

Definition at line 200 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)

Definition at line 189 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f

Definition at line 193 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5

Definition at line 192 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)

Definition at line 198 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)

Definition at line 190 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f

Definition at line 195 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10

Definition at line 194 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)

Definition at line 199 of file ar71xx_regs.h.

#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08

Definition at line 169 of file ar71xx_regs.h.

#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff

Definition at line 181 of file ar71xx_regs.h.

#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0

Definition at line 180 of file ar71xx_regs.h.

#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f

Definition at line 183 of file ar71xx_regs.h.

#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10

Definition at line 182 of file ar71xx_regs.h.

#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7

Definition at line 187 of file ar71xx_regs.h.

#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23

Definition at line 186 of file ar71xx_regs.h.

#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f

Definition at line 185 of file ar71xx_regs.h.

#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16

Definition at line 184 of file ar71xx_regs.h.

#define AR934X_PLL_DDR_CONFIG_REG 0x04

Definition at line 168 of file ar71xx_regs.h.

#define AR934X_RESET_REG_BOOTSTRAP 0xb0

Definition at line 238 of file ar71xx_regs.h.

#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac

Definition at line 239 of file ar71xx_regs.h.

#define AR934X_RESET_REG_RESET_MODULE 0x1c

Definition at line 237 of file ar71xx_regs.h.

#define AR934X_RESET_USB_HOST BIT(5)

Definition at line 296 of file ar71xx_regs.h.

#define AR934X_RESET_USB_PHY BIT(4)

Definition at line 297 of file ar71xx_regs.h.

#define AR934X_RESET_USB_PHY_ANALOG BIT(11)

Definition at line 295 of file ar71xx_regs.h.

#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)

Definition at line 298 of file ar71xx_regs.h.

#define AR934X_REV_ID_REVISION_MASK 0xf

Definition at line 365 of file ar71xx_regs.h.

#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)

Definition at line 68 of file ar71xx_regs.h.

#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0

Definition at line 414 of file ar71xx_regs.h.

#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4

Definition at line 415 of file ar71xx_regs.h.

#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8

Definition at line 416 of file ar71xx_regs.h.

#define AR934X_SRIF_DDR_DPLL1_REG 0x240

Definition at line 418 of file ar71xx_regs.h.

#define AR934X_SRIF_DDR_DPLL2_REG 0x244

Definition at line 419 of file ar71xx_regs.h.

#define AR934X_SRIF_DDR_DPLL3_REG 0x248

Definition at line 420 of file ar71xx_regs.h.

#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff

Definition at line 426 of file ar71xx_regs.h.

#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff

Definition at line 425 of file ar71xx_regs.h.

#define AR934X_SRIF_DPLL1_NINT_SHIFT 18

Definition at line 424 of file ar71xx_regs.h.

#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f

Definition at line 423 of file ar71xx_regs.h.

#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27

Definition at line 422 of file ar71xx_regs.h.

#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30)

Definition at line 428 of file ar71xx_regs.h.

#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7

Definition at line 430 of file ar71xx_regs.h.

#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13

Definition at line 429 of file ar71xx_regs.h.

#define AR934X_SRIF_SIZE 0x1000

Definition at line 69 of file ar71xx_regs.h.

#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)

Definition at line 64 of file ar71xx_regs.h.

#define AR934X_WMAC_SIZE 0x20000

Definition at line 65 of file ar71xx_regs.h.

#define MISC_INT_DMA BIT(7)

Definition at line 245 of file ar71xx_regs.h.

#define MISC_INT_ERROR BIT(1)

Definition at line 251 of file ar71xx_regs.h.

#define MISC_INT_ETHSW BIT(12)

Definition at line 241 of file ar71xx_regs.h.

#define MISC_INT_GPIO BIT(2)

Definition at line 250 of file ar71xx_regs.h.

#define MISC_INT_OHCI BIT(6)

Definition at line 246 of file ar71xx_regs.h.

#define MISC_INT_PERFC BIT(5)

Definition at line 247 of file ar71xx_regs.h.

#define MISC_INT_TIMER BIT(0)

Definition at line 252 of file ar71xx_regs.h.

#define MISC_INT_TIMER2 BIT(8)

Definition at line 244 of file ar71xx_regs.h.

#define MISC_INT_TIMER3 BIT(9)

Definition at line 243 of file ar71xx_regs.h.

#define MISC_INT_TIMER4 BIT(10)

Definition at line 242 of file ar71xx_regs.h.

#define MISC_INT_UART BIT(3)

Definition at line 249 of file ar71xx_regs.h.

#define MISC_INT_WDOG BIT(4)

Definition at line 248 of file ar71xx_regs.h.

#define REV_ID_MAJOR_AR71XX 0x00a0

Definition at line 337 of file ar71xx_regs.h.

#define REV_ID_MAJOR_AR7240 0x00c0

Definition at line 339 of file ar71xx_regs.h.

#define REV_ID_MAJOR_AR7241 0x0100

Definition at line 340 of file ar71xx_regs.h.

#define REV_ID_MAJOR_AR7242 0x1100

Definition at line 341 of file ar71xx_regs.h.

#define REV_ID_MAJOR_AR913X 0x00b0

Definition at line 338 of file ar71xx_regs.h.

#define REV_ID_MAJOR_AR9330 0x0110

Definition at line 342 of file ar71xx_regs.h.

#define REV_ID_MAJOR_AR9331 0x1110

Definition at line 343 of file ar71xx_regs.h.

#define REV_ID_MAJOR_AR9341 0x0120

Definition at line 344 of file ar71xx_regs.h.

#define REV_ID_MAJOR_AR9342 0x1120

Definition at line 345 of file ar71xx_regs.h.

#define REV_ID_MAJOR_AR9344 0x2120

Definition at line 346 of file ar71xx_regs.h.

#define REV_ID_MAJOR_MASK 0xfff0

Definition at line 336 of file ar71xx_regs.h.

Macros

Macro Definition Documentation