|
#define | ADMA_ACCR(chan) (chan->mmr_base + 0x0) |
|
#define | ADMA_ACSR(chan) (chan->mmr_base + 0x4) |
|
#define | ADMA_ADAR(chan) (chan->mmr_base + 0x8) |
|
#define | ADMA_IIPCR(chan) (chan->mmr_base + 0x18) |
|
#define | ADMA_IIPAR(chan) (chan->mmr_base + 0x1c) |
|
#define | ADMA_IIPUAR(chan) (chan->mmr_base + 0x20) |
|
#define | ADMA_ANDAR(chan) (chan->mmr_base + 0x24) |
|
#define | ADMA_ADCR(chan) (chan->mmr_base + 0x28) |
|
#define | ADMA_CARMD(chan) (chan->mmr_base + 0x2c) |
|
#define | ADMA_ABCR(chan) (chan->mmr_base + 0x30) |
|
#define | ADMA_DLADR(chan) (chan->mmr_base + 0x34) |
|
#define | ADMA_DUADR(chan) (chan->mmr_base + 0x38) |
|
#define | ADMA_SLAR(src, chan) (chan->mmr_base + (0x3c + (src << 3))) |
|
#define | ADMA_SUAR(src, chan) (chan->mmr_base + (0x40 + (src << 3))) |
|
#define | iop_adma_get_max_pq iop_adma_get_max_xor |
|
#define | ADMA_STATUS_BUSY (1 << 13) |
|
#define | iop_desc_is_aligned(x, y) 1 |
|
#define | iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s) |
|
#define | ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024) |
|
#define | IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT |
|
#define | IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT |
|
#define | IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT |
|
#define | IOP_ADMA_PQ_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT |
|
#define | iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o) |
|
#define | iop_chan_pq_slot_count iop_chan_xor_slot_count |
|
#define | iop_chan_pq_zero_sum_slot_count iop_chan_xor_slot_count |
|
#define | iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i) |
|
#define | iop_desc_set_pq_zero_sum_byte_count iop_desc_set_zero_sum_byte_count |
|
#define | iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr |
|
#define | iop_desc_set_pq_zero_sum_src_addr iop_desc_set_pq_src_addr |
|