pcie.c File Reference

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <asm/sizes.h>
#include <asm/mach/pci.h>
#include <mach/iomap.h>
#include <mach/clk.h>
#include <mach/powergate.h>
#include "board.h"

Go to the source code of this file.

Data Structures
struct	tegra_pcie_port
struct	tegra_pcie_info

Macros
#define	AFI_OFFSET   0x3800
#define	PADS_OFFSET   0x3000
#define	RP0_OFFSET   0x0000
#define	RP1_OFFSET   0x1000
#define	AFI_AXI_BAR0_SZ   0x00
#define	AFI_AXI_BAR1_SZ   0x04
#define	AFI_AXI_BAR2_SZ   0x08
#define	AFI_AXI_BAR3_SZ   0x0c
#define	AFI_AXI_BAR4_SZ   0x10
#define	AFI_AXI_BAR5_SZ   0x14
#define	AFI_AXI_BAR0_START   0x18
#define	AFI_AXI_BAR1_START   0x1c
#define	AFI_AXI_BAR2_START   0x20
#define	AFI_AXI_BAR3_START   0x24
#define	AFI_AXI_BAR4_START   0x28
#define	AFI_AXI_BAR5_START   0x2c
#define	AFI_FPCI_BAR0   0x30
#define	AFI_FPCI_BAR1   0x34
#define	AFI_FPCI_BAR2   0x38
#define	AFI_FPCI_BAR3   0x3c
#define	AFI_FPCI_BAR4   0x40
#define	AFI_FPCI_BAR5   0x44
#define	AFI_CACHE_BAR0_SZ   0x48
#define	AFI_CACHE_BAR0_ST   0x4c
#define	AFI_CACHE_BAR1_SZ   0x50
#define	AFI_CACHE_BAR1_ST   0x54
#define	AFI_MSI_BAR_SZ   0x60
#define	AFI_MSI_FPCI_BAR_ST   0x64
#define	AFI_MSI_AXI_BAR_ST   0x68
#define	AFI_CONFIGURATION   0xac
#define	AFI_CONFIGURATION_EN_FPCI   (1 << 0)
#define	AFI_FPCI_ERROR_MASKS   0xb0
#define	AFI_INTR_MASK   0xb4
#define	AFI_INTR_MASK_INT_MASK   (1 << 0)
#define	AFI_INTR_MASK_MSI_MASK   (1 << 8)
#define	AFI_INTR_CODE   0xb8
#define	AFI_INTR_CODE_MASK   0xf
#define	AFI_INTR_MASTER_ABORT   4
#define	AFI_INTR_LEGACY   6
#define	AFI_INTR_SIGNATURE   0xbc
#define	AFI_SM_INTR_ENABLE   0xc4
#define	AFI_AFI_INTR_ENABLE   0xc8
#define	AFI_INTR_EN_INI_SLVERR   (1 << 0)
#define	AFI_INTR_EN_INI_DECERR   (1 << 1)
#define	AFI_INTR_EN_TGT_SLVERR   (1 << 2)
#define	AFI_INTR_EN_TGT_DECERR   (1 << 3)
#define	AFI_INTR_EN_TGT_WRERR   (1 << 4)
#define	AFI_INTR_EN_DFPCI_DECERR   (1 << 5)
#define	AFI_INTR_EN_AXI_DECERR   (1 << 6)
#define	AFI_INTR_EN_FPCI_TIMEOUT   (1 << 7)
#define	AFI_PCIE_CONFIG   0x0f8
#define	AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE   (1 << 1)
#define	AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE   (1 << 2)
#define	AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK   (0xf << 20)
#define	AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE   (0x0 << 20)
#define	AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL   (0x1 << 20)
#define	AFI_FUSE   0x104
#define	AFI_FUSE_PCIE_T0_GEN2_DIS   (1 << 2)
#define	AFI_PEX0_CTRL   0x110
#define	AFI_PEX1_CTRL   0x118
#define	AFI_PEX_CTRL_RST   (1 << 0)
#define	AFI_PEX_CTRL_REFCLK_EN   (1 << 3)
#define	RP_VEND_XP   0x00000F00
#define	RP_VEND_XP_DL_UP   (1 << 30)
#define	RP_LINK_CONTROL_STATUS   0x00000090
#define	RP_LINK_CONTROL_STATUS_LINKSTAT_MASK   0x3fff0000
#define	PADS_CTL_SEL   0x0000009C
#define	PADS_CTL   0x000000A0
#define	PADS_CTL_IDDQ_1L   (1 << 0)
#define	PADS_CTL_TX_DATA_EN_1L   (1 << 6)
#define	PADS_CTL_RX_DATA_EN_1L   (1 << 10)
#define	PADS_PLL_CTL   0x000000B8
#define	PADS_PLL_CTL_RST_B4SM   (1 << 1)
#define	PADS_PLL_CTL_LOCKDET   (1 << 8)
#define	PADS_PLL_CTL_REFCLK_MASK   (0x3 << 16)
#define	PADS_PLL_CTL_REFCLK_INTERNAL_CML   (0 << 16)
#define	PADS_PLL_CTL_REFCLK_INTERNAL_CMOS   (1 << 16)
#define	PADS_PLL_CTL_REFCLK_EXTERNAL   (2 << 16)
#define	PADS_PLL_CTL_TXCLKREF_MASK   (0x1 << 20)
#define	PADS_PLL_CTL_TXCLKREF_DIV10   (0 << 20)
#define	PADS_PLL_CTL_TXCLKREF_DIV5   (1 << 20)
#define	PMC_SCRATCH42   0x144
#define	PMC_SCRATCH42_PCX_CLAMP   (1 << 0)
#define	pmc_writel(value, reg)   __raw_writel(value, reg_pmc_base + (reg))
#define	pmc_readl(reg)   __raw_readl(reg_pmc_base + (reg))
#define	PCIE_REGS_SZ   SZ_16K
#define	PCIE_CFG_OFF   PCIE_REGS_SZ
#define	PCIE_CFG_SZ   SZ_1M
#define	PCIE_EXT_CFG_OFF   (PCIE_CFG_SZ + PCIE_CFG_OFF)
#define	PCIE_EXT_CFG_SZ   SZ_1M
#define	PCIE_IOMAP_SZ   (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
#define	MEM_BASE_0   (TEGRA_PCIE_BASE + SZ_256M)
#define	MEM_SIZE_0   SZ_128M
#define	MEM_BASE_1   (MEM_BASE_0 + MEM_SIZE_0)
#define	MEM_SIZE_1   SZ_128M
#define	PREFETCH_MEM_BASE_0   (MEM_BASE_1 + MEM_SIZE_1)
#define	PREFETCH_MEM_SIZE_0   SZ_128M
#define	PREFETCH_MEM_BASE_1   (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0)
#define	PREFETCH_MEM_SIZE_1   SZ_128M
#define	PCIE_CONF_BUS(b)   ((b) << 16)
#define	PCIE_CONF_DEV(d)   ((d) << 11)
#define	PCIE_CONF_FUNC(f)   ((f) << 8)
#define	PCIE_CONF_REG(r)   (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF))
#define	TEGRA_PCIE_LINKUP_TIMEOUT   200 /* up to 1.2 seconds */

Functions
	DECLARE_PCI_FIXUP_FINAL (PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge)
	DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class)
	DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class)
	DECLARE_PCI_FIXUP_FINAL (PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable)
int __init	tegra_pcie_init (bool init_port0, bool init_port1)

Macro Definition Documentation

#define AFI_AFI_INTR_ENABLE   0xc8

Definition at line 99 of file pcie.c.

#define AFI_AXI_BAR0_START   0x18

Definition at line 59 of file pcie.c.

#define AFI_AXI_BAR0_SZ   0x00

Definition at line 52 of file pcie.c.

#define AFI_AXI_BAR1_START   0x1c

Definition at line 60 of file pcie.c.

#define AFI_AXI_BAR1_SZ   0x04

Definition at line 53 of file pcie.c.

#define AFI_AXI_BAR2_START   0x20

Definition at line 61 of file pcie.c.

#define AFI_AXI_BAR2_SZ   0x08

Definition at line 54 of file pcie.c.

#define AFI_AXI_BAR3_START   0x24

Definition at line 62 of file pcie.c.

#define AFI_AXI_BAR3_SZ   0x0c

Definition at line 55 of file pcie.c.

#define AFI_AXI_BAR4_START   0x28

Definition at line 63 of file pcie.c.

#define AFI_AXI_BAR4_SZ   0x10

Definition at line 56 of file pcie.c.

#define AFI_AXI_BAR5_START   0x2c

Definition at line 64 of file pcie.c.

#define AFI_AXI_BAR5_SZ   0x14

Definition at line 57 of file pcie.c.

#define AFI_CACHE_BAR0_ST   0x4c

Definition at line 74 of file pcie.c.

#define AFI_CACHE_BAR0_SZ   0x48

Definition at line 73 of file pcie.c.

#define AFI_CACHE_BAR1_ST   0x54

Definition at line 76 of file pcie.c.

#define AFI_CACHE_BAR1_SZ   0x50

Definition at line 75 of file pcie.c.

#define AFI_CONFIGURATION   0xac

Definition at line 82 of file pcie.c.

#define AFI_CONFIGURATION_EN_FPCI   (1 << 0)

Definition at line 83 of file pcie.c.

#define AFI_FPCI_BAR0   0x30

Definition at line 66 of file pcie.c.

#define AFI_FPCI_BAR1   0x34

Definition at line 67 of file pcie.c.

#define AFI_FPCI_BAR2   0x38

Definition at line 68 of file pcie.c.

#define AFI_FPCI_BAR3   0x3c

Definition at line 69 of file pcie.c.

#define AFI_FPCI_BAR4   0x40

Definition at line 70 of file pcie.c.

#define AFI_FPCI_BAR5   0x44

Definition at line 71 of file pcie.c.

#define AFI_FPCI_ERROR_MASKS   0xb0

Definition at line 85 of file pcie.c.

#define AFI_FUSE   0x104

Definition at line 116 of file pcie.c.

#define AFI_FUSE_PCIE_T0_GEN2_DIS   (1 << 2)

Definition at line 117 of file pcie.c.

#define AFI_INTR_CODE   0xb8

Definition at line 91 of file pcie.c.

#define AFI_INTR_CODE_MASK   0xf

Definition at line 92 of file pcie.c.

#define AFI_INTR_EN_AXI_DECERR   (1 << 6)

Definition at line 106 of file pcie.c.

#define AFI_INTR_EN_DFPCI_DECERR   (1 << 5)

Definition at line 105 of file pcie.c.

#define AFI_INTR_EN_FPCI_TIMEOUT   (1 << 7)

Definition at line 107 of file pcie.c.

#define AFI_INTR_EN_INI_DECERR   (1 << 1)

Definition at line 101 of file pcie.c.

#define AFI_INTR_EN_INI_SLVERR   (1 << 0)

Definition at line 100 of file pcie.c.

#define AFI_INTR_EN_TGT_DECERR   (1 << 3)

Definition at line 103 of file pcie.c.

#define AFI_INTR_EN_TGT_SLVERR   (1 << 2)

Definition at line 102 of file pcie.c.

#define AFI_INTR_EN_TGT_WRERR   (1 << 4)

Definition at line 104 of file pcie.c.

#define AFI_INTR_LEGACY   6

Definition at line 94 of file pcie.c.

#define AFI_INTR_MASK   0xb4

Definition at line 87 of file pcie.c.

#define AFI_INTR_MASK_INT_MASK   (1 << 0)

Definition at line 88 of file pcie.c.

#define AFI_INTR_MASK_MSI_MASK   (1 << 8)

Definition at line 89 of file pcie.c.

#define AFI_INTR_MASTER_ABORT   4

Definition at line 93 of file pcie.c.

#define AFI_INTR_SIGNATURE   0xbc

Definition at line 96 of file pcie.c.

#define AFI_MSI_AXI_BAR_ST   0x68

Definition at line 80 of file pcie.c.

#define AFI_MSI_BAR_SZ   0x60

Definition at line 78 of file pcie.c.

#define AFI_MSI_FPCI_BAR_ST   0x64

Definition at line 79 of file pcie.c.

#define AFI_OFFSET   0x3800

Definition at line 47 of file pcie.c.

#define AFI_PCIE_CONFIG   0x0f8

Definition at line 109 of file pcie.c.

#define AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE   (1 << 1)

Definition at line 110 of file pcie.c.

#define AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE   (1 << 2)

Definition at line 111 of file pcie.c.

#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL   (0x1 << 20)

Definition at line 114 of file pcie.c.

#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK   (0xf << 20)

Definition at line 112 of file pcie.c.

#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE   (0x0 << 20)

Definition at line 113 of file pcie.c.

#define AFI_PEX0_CTRL   0x110

Definition at line 119 of file pcie.c.

#define AFI_PEX1_CTRL   0x118

Definition at line 120 of file pcie.c.

#define AFI_PEX_CTRL_REFCLK_EN   (1 << 3)

Definition at line 122 of file pcie.c.

#define AFI_PEX_CTRL_RST   (1 << 0)

Definition at line 121 of file pcie.c.

#define AFI_SM_INTR_ENABLE   0xc4

Definition at line 97 of file pcie.c.

#define MEM_BASE_0   (TEGRA_PCIE_BASE + SZ_256M)

Definition at line 181 of file pcie.c.

#define MEM_BASE_1   (MEM_BASE_0 + MEM_SIZE_0)

Definition at line 183 of file pcie.c.

#define MEM_SIZE_0   SZ_128M

Definition at line 182 of file pcie.c.

#define MEM_SIZE_1   SZ_128M

Definition at line 184 of file pcie.c.

#define PADS_CTL   0x000000A0

Definition at line 132 of file pcie.c.

#define PADS_CTL_IDDQ_1L   (1 << 0)

Definition at line 133 of file pcie.c.

#define PADS_CTL_RX_DATA_EN_1L   (1 << 10)

Definition at line 135 of file pcie.c.

#define PADS_CTL_SEL   0x0000009C

Definition at line 130 of file pcie.c.

#define PADS_CTL_TX_DATA_EN_1L   (1 << 6)

Definition at line 134 of file pcie.c.

#define PADS_OFFSET   0x3000

Definition at line 48 of file pcie.c.

#define PADS_PLL_CTL   0x000000B8

Definition at line 137 of file pcie.c.

#define PADS_PLL_CTL_LOCKDET   (1 << 8)

Definition at line 139 of file pcie.c.

#define PADS_PLL_CTL_REFCLK_EXTERNAL   (2 << 16)

Definition at line 143 of file pcie.c.

#define PADS_PLL_CTL_REFCLK_INTERNAL_CML   (0 << 16)

Definition at line 141 of file pcie.c.

#define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS   (1 << 16)

Definition at line 142 of file pcie.c.

#define PADS_PLL_CTL_REFCLK_MASK   (0x3 << 16)

Definition at line 140 of file pcie.c.

#define PADS_PLL_CTL_RST_B4SM   (1 << 1)

Definition at line 138 of file pcie.c.

#define PADS_PLL_CTL_TXCLKREF_DIV10   (0 << 20)

Definition at line 145 of file pcie.c.

#define PADS_PLL_CTL_TXCLKREF_DIV5   (1 << 20)

Definition at line 146 of file pcie.c.

#define PADS_PLL_CTL_TXCLKREF_MASK   (0x1 << 20)

Definition at line 144 of file pcie.c.

#define PCIE_CFG_OFF   PCIE_REGS_SZ

Definition at line 175 of file pcie.c.

#define PCIE_CFG_SZ   SZ_1M

Definition at line 176 of file pcie.c.

#define PCIE_CONF_BUS

(

b

)

((b) << 16)

Definition at line 190 of file pcie.c.

#define PCIE_CONF_DEV

(

d

)

((d) << 11)

Definition at line 191 of file pcie.c.

#define PCIE_CONF_FUNC

(

f

)

((f) << 8)

Definition at line 192 of file pcie.c.

#define PCIE_CONF_REG

(

r

)

(((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF))

Definition at line 193 of file pcie.c.

#define PCIE_EXT_CFG_OFF   (PCIE_CFG_SZ + PCIE_CFG_OFF)

Definition at line 177 of file pcie.c.

#define PCIE_EXT_CFG_SZ   SZ_1M

Definition at line 178 of file pcie.c.

#define PCIE_IOMAP_SZ   (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)

Definition at line 179 of file pcie.c.

#define PCIE_REGS_SZ   SZ_16K

Definition at line 174 of file pcie.c.

#define pmc_readl

(

reg

)

__raw_readl(reg_pmc_base + (reg))

Definition at line 156 of file pcie.c.

#define PMC_SCRATCH42   0x144

Definition at line 149 of file pcie.c.

#define PMC_SCRATCH42_PCX_CLAMP   (1 << 0)

Definition at line 150 of file pcie.c.

#define pmc_writel	(		value,
			reg
	)		__raw_writel(value, reg_pmc_base + (reg))

Definition at line 154 of file pcie.c.

#define PREFETCH_MEM_BASE_0   (MEM_BASE_1 + MEM_SIZE_1)

Definition at line 185 of file pcie.c.

#define PREFETCH_MEM_BASE_1   (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0)

Definition at line 187 of file pcie.c.

#define PREFETCH_MEM_SIZE_0   SZ_128M

Definition at line 186 of file pcie.c.

#define PREFETCH_MEM_SIZE_1   SZ_128M

Definition at line 188 of file pcie.c.

#define RP0_OFFSET   0x0000

Definition at line 49 of file pcie.c.

#define RP1_OFFSET   0x1000

Definition at line 50 of file pcie.c.

#define RP_LINK_CONTROL_STATUS   0x00000090

Definition at line 127 of file pcie.c.

#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK   0x3fff0000

Definition at line 128 of file pcie.c.

#define RP_VEND_XP   0x00000F00

Definition at line 124 of file pcie.c.

#define RP_VEND_XP_DL_UP   (1 << 30)

Definition at line 125 of file pcie.c.

#define TEGRA_PCIE_LINKUP_TIMEOUT   200 /* up to 1.2 seconds */

Definition at line 783 of file pcie.c.

Function Documentation

DECLARE_PCI_FIXUP_EARLY	(	PCI_VENDOR_ID_NVIDIA	,
		0x0bf0	,
		tegra_pcie_fixup_class
	)

DECLARE_PCI_FIXUP_EARLY	(	PCI_VENDOR_ID_NVIDIA	,
		0x0bf1	,
		tegra_pcie_fixup_class
	)

DECLARE_PCI_FIXUP_FINAL	(	PCI_ANY_ID	,
		PCI_ANY_ID	,
		tegra_pcie_fixup_bridge
	)

DECLARE_PCI_FIXUP_FINAL	(	PCI_ANY_ID	,
		PCI_ANY_ID	,
		tegra_pcie_relax_enable
	)

int __init tegra_pcie_init	(	bool	init_port0,
		bool	init_port1
	)

Definition at line 855 of file pcie.c.