Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
timer.c
Go to the documentation of this file.
1 /*
2  *
3  * arch/arm/mach-u300/timer.c
4  *
5  *
6  * Copyright (C) 2007-2009 ST-Ericsson AB
7  * License terms: GNU General Public License (GPL) version 2
8  * Timer COH 901 328, runs the OS timer interrupt.
9  * Author: Linus Walleij <[email protected]>
10  */
11 #include <linux/interrupt.h>
12 #include <linux/time.h>
13 #include <linux/timex.h>
14 #include <linux/clockchips.h>
15 #include <linux/clocksource.h>
16 #include <linux/types.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/err.h>
20 #include <linux/irq.h>
21 
22 #include <mach/hardware.h>
23 #include <mach/irqs.h>
24 
25 /* Generic stuff */
26 #include <asm/sched_clock.h>
27 #include <asm/mach/map.h>
28 #include <asm/mach/time.h>
29 
30 #include "timer.h"
31 
32 /*
33  * APP side special timer registers
34  * This timer contains four timers which can fire an interrupt each.
35  * OS (operating system) timer @ 32768 Hz
36  * DD (device driver) timer @ 1 kHz
37  * GP1 (general purpose 1) timer @ 1MHz
38  * GP2 (general purpose 2) timer @ 1MHz
39  */
40 
41 /* Reset OS Timer 32bit (-/W) */
42 #define U300_TIMER_APP_ROST (0x0000)
43 #define U300_TIMER_APP_ROST_TIMER_RESET (0x00000000)
44 /* Enable OS Timer 32bit (-/W) */
45 #define U300_TIMER_APP_EOST (0x0004)
46 #define U300_TIMER_APP_EOST_TIMER_ENABLE (0x00000000)
47 /* Disable OS Timer 32bit (-/W) */
48 #define U300_TIMER_APP_DOST (0x0008)
49 #define U300_TIMER_APP_DOST_TIMER_DISABLE (0x00000000)
50 /* OS Timer Mode Register 32bit (-/W) */
51 #define U300_TIMER_APP_SOSTM (0x000c)
52 #define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS (0x00000000)
53 #define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT (0x00000001)
54 /* OS Timer Status Register 32bit (R/-) */
55 #define U300_TIMER_APP_OSTS (0x0010)
56 #define U300_TIMER_APP_OSTS_TIMER_STATE_MASK (0x0000000F)
57 #define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE (0x00000001)
58 #define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE (0x00000002)
59 #define U300_TIMER_APP_OSTS_ENABLE_IND (0x00000010)
60 #define U300_TIMER_APP_OSTS_MODE_MASK (0x00000020)
61 #define U300_TIMER_APP_OSTS_MODE_CONTINUOUS (0x00000000)
62 #define U300_TIMER_APP_OSTS_MODE_ONE_SHOT (0x00000020)
63 #define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND (0x00000040)
64 #define U300_TIMER_APP_OSTS_IRQ_PENDING_IND (0x00000080)
65 /* OS Timer Current Count Register 32bit (R/-) */
66 #define U300_TIMER_APP_OSTCC (0x0014)
67 /* OS Timer Terminal Count Register 32bit (R/W) */
68 #define U300_TIMER_APP_OSTTC (0x0018)
69 /* OS Timer Interrupt Enable Register 32bit (-/W) */
70 #define U300_TIMER_APP_OSTIE (0x001c)
71 #define U300_TIMER_APP_OSTIE_IRQ_DISABLE (0x00000000)
72 #define U300_TIMER_APP_OSTIE_IRQ_ENABLE (0x00000001)
73 /* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
74 #define U300_TIMER_APP_OSTIA (0x0020)
75 #define U300_TIMER_APP_OSTIA_IRQ_ACK (0x00000080)
76 
77 /* Reset DD Timer 32bit (-/W) */
78 #define U300_TIMER_APP_RDDT (0x0040)
79 #define U300_TIMER_APP_RDDT_TIMER_RESET (0x00000000)
80 /* Enable DD Timer 32bit (-/W) */
81 #define U300_TIMER_APP_EDDT (0x0044)
82 #define U300_TIMER_APP_EDDT_TIMER_ENABLE (0x00000000)
83 /* Disable DD Timer 32bit (-/W) */
84 #define U300_TIMER_APP_DDDT (0x0048)
85 #define U300_TIMER_APP_DDDT_TIMER_DISABLE (0x00000000)
86 /* DD Timer Mode Register 32bit (-/W) */
87 #define U300_TIMER_APP_SDDTM (0x004c)
88 #define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS (0x00000000)
89 #define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT (0x00000001)
90 /* DD Timer Status Register 32bit (R/-) */
91 #define U300_TIMER_APP_DDTS (0x0050)
92 #define U300_TIMER_APP_DDTS_TIMER_STATE_MASK (0x0000000F)
93 #define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE (0x00000001)
94 #define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE (0x00000002)
95 #define U300_TIMER_APP_DDTS_ENABLE_IND (0x00000010)
96 #define U300_TIMER_APP_DDTS_MODE_MASK (0x00000020)
97 #define U300_TIMER_APP_DDTS_MODE_CONTINUOUS (0x00000000)
98 #define U300_TIMER_APP_DDTS_MODE_ONE_SHOT (0x00000020)
99 #define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND (0x00000040)
100 #define U300_TIMER_APP_DDTS_IRQ_PENDING_IND (0x00000080)
101 /* DD Timer Current Count Register 32bit (R/-) */
102 #define U300_TIMER_APP_DDTCC (0x0054)
103 /* DD Timer Terminal Count Register 32bit (R/W) */
104 #define U300_TIMER_APP_DDTTC (0x0058)
105 /* DD Timer Interrupt Enable Register 32bit (-/W) */
106 #define U300_TIMER_APP_DDTIE (0x005c)
107 #define U300_TIMER_APP_DDTIE_IRQ_DISABLE (0x00000000)
108 #define U300_TIMER_APP_DDTIE_IRQ_ENABLE (0x00000001)
109 /* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
110 #define U300_TIMER_APP_DDTIA (0x0060)
111 #define U300_TIMER_APP_DDTIA_IRQ_ACK (0x00000080)
112 
113 /* Reset GP1 Timer 32bit (-/W) */
114 #define U300_TIMER_APP_RGPT1 (0x0080)
115 #define U300_TIMER_APP_RGPT1_TIMER_RESET (0x00000000)
116 /* Enable GP1 Timer 32bit (-/W) */
117 #define U300_TIMER_APP_EGPT1 (0x0084)
118 #define U300_TIMER_APP_EGPT1_TIMER_ENABLE (0x00000000)
119 /* Disable GP1 Timer 32bit (-/W) */
120 #define U300_TIMER_APP_DGPT1 (0x0088)
121 #define U300_TIMER_APP_DGPT1_TIMER_DISABLE (0x00000000)
122 /* GP1 Timer Mode Register 32bit (-/W) */
123 #define U300_TIMER_APP_SGPT1M (0x008c)
124 #define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS (0x00000000)
125 #define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT (0x00000001)
126 /* GP1 Timer Status Register 32bit (R/-) */
127 #define U300_TIMER_APP_GPT1S (0x0090)
128 #define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK (0x0000000F)
129 #define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE (0x00000001)
130 #define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE (0x00000002)
131 #define U300_TIMER_APP_GPT1S_ENABLE_IND (0x00000010)
132 #define U300_TIMER_APP_GPT1S_MODE_MASK (0x00000020)
133 #define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS (0x00000000)
134 #define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT (0x00000020)
135 #define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND (0x00000040)
136 #define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND (0x00000080)
137 /* GP1 Timer Current Count Register 32bit (R/-) */
138 #define U300_TIMER_APP_GPT1CC (0x0094)
139 /* GP1 Timer Terminal Count Register 32bit (R/W) */
140 #define U300_TIMER_APP_GPT1TC (0x0098)
141 /* GP1 Timer Interrupt Enable Register 32bit (-/W) */
142 #define U300_TIMER_APP_GPT1IE (0x009c)
143 #define U300_TIMER_APP_GPT1IE_IRQ_DISABLE (0x00000000)
144 #define U300_TIMER_APP_GPT1IE_IRQ_ENABLE (0x00000001)
145 /* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
146 #define U300_TIMER_APP_GPT1IA (0x00a0)
147 #define U300_TIMER_APP_GPT1IA_IRQ_ACK (0x00000080)
148 
149 /* Reset GP2 Timer 32bit (-/W) */
150 #define U300_TIMER_APP_RGPT2 (0x00c0)
151 #define U300_TIMER_APP_RGPT2_TIMER_RESET (0x00000000)
152 /* Enable GP2 Timer 32bit (-/W) */
153 #define U300_TIMER_APP_EGPT2 (0x00c4)
154 #define U300_TIMER_APP_EGPT2_TIMER_ENABLE (0x00000000)
155 /* Disable GP2 Timer 32bit (-/W) */
156 #define U300_TIMER_APP_DGPT2 (0x00c8)
157 #define U300_TIMER_APP_DGPT2_TIMER_DISABLE (0x00000000)
158 /* GP2 Timer Mode Register 32bit (-/W) */
159 #define U300_TIMER_APP_SGPT2M (0x00cc)
160 #define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS (0x00000000)
161 #define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT (0x00000001)
162 /* GP2 Timer Status Register 32bit (R/-) */
163 #define U300_TIMER_APP_GPT2S (0x00d0)
164 #define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK (0x0000000F)
165 #define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE (0x00000001)
166 #define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE (0x00000002)
167 #define U300_TIMER_APP_GPT2S_ENABLE_IND (0x00000010)
168 #define U300_TIMER_APP_GPT2S_MODE_MASK (0x00000020)
169 #define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS (0x00000000)
170 #define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT (0x00000020)
171 #define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND (0x00000040)
172 #define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND (0x00000080)
173 /* GP2 Timer Current Count Register 32bit (R/-) */
174 #define U300_TIMER_APP_GPT2CC (0x00d4)
175 /* GP2 Timer Terminal Count Register 32bit (R/W) */
176 #define U300_TIMER_APP_GPT2TC (0x00d8)
177 /* GP2 Timer Interrupt Enable Register 32bit (-/W) */
178 #define U300_TIMER_APP_GPT2IE (0x00dc)
179 #define U300_TIMER_APP_GPT2IE_IRQ_DISABLE (0x00000000)
180 #define U300_TIMER_APP_GPT2IE_IRQ_ENABLE (0x00000001)
181 /* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
182 #define U300_TIMER_APP_GPT2IA (0x00e0)
183 #define U300_TIMER_APP_GPT2IA_IRQ_ACK (0x00000080)
184 
185 /* Clock request control register - all four timers */
186 #define U300_TIMER_APP_CRC (0x100)
187 #define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE (0x00000001)
188 
189 #define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
190 #define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
191 
192 /*
193  * The u300_set_mode() function is always called first, if we
194  * have oneshot timer active, the oneshot scheduling function
195  * u300_set_next_event() is called immediately after.
196  */
197 static void u300_set_mode(enum clock_event_mode mode,
198  struct clock_event_device *evt)
199 {
200  switch (mode) {
201  case CLOCK_EVT_MODE_PERIODIC:
202  /* Disable interrupts on GPT1 */
203  writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
204  U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
205  /* Disable GP1 while we're reprogramming it. */
206  writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
207  U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
208  /*
209  * Set the periodic mode to a certain number of ticks per
210  * jiffy.
211  */
212  writel(TICKS_PER_JIFFY,
213  U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
214  /*
215  * Set continuous mode, so the timer keeps triggering
216  * interrupts.
217  */
218  writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
219  U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
220  /* Enable timer interrupts */
221  writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
222  U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
223  /* Then enable the OS timer again */
224  writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
225  U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
226  break;
227  case CLOCK_EVT_MODE_ONESHOT:
228  /* Just break; here? */
229  /*
230  * The actual event will be programmed by the next event hook,
231  * so we just set a dummy value somewhere at the end of the
232  * universe here.
233  */
234  /* Disable interrupts on GPT1 */
235  writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
236  U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
237  /* Disable GP1 while we're reprogramming it. */
238  writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
239  U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
240  /*
241  * Expire far in the future, u300_set_next_event() will be
242  * called soon...
243  */
244  writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
245  /* We run one shot per tick here! */
246  writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
247  U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
248  /* Enable interrupts for this timer */
249  writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
250  U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
251  /* Enable timer */
252  writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
253  U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
254  break;
255  case CLOCK_EVT_MODE_UNUSED:
256  case CLOCK_EVT_MODE_SHUTDOWN:
257  /* Disable interrupts on GP1 */
258  writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
259  U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
260  /* Disable GP1 */
261  writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
262  U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
263  break;
264  case CLOCK_EVT_MODE_RESUME:
265  /* Ignore this call */
266  break;
267  }
268 }
269 
270 /*
271  * The app timer in one shot mode obviously has to be reprogrammed
272  * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
273  * the interrupt disable + timer disable commands with a reset command,
274  * it will fail miserably. Apparently (and I found this the hard way)
275  * the timer is very sensitive to the instruction order, though you don't
276  * get that impression from the data sheet.
277  */
278 static int u300_set_next_event(unsigned long cycles,
279  struct clock_event_device *evt)
280 
281 {
282  /* Disable interrupts on GPT1 */
283  writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
284  U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
285  /* Disable GP1 while we're reprogramming it. */
286  writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
287  U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
288  /* Reset the General Purpose timer 1. */
289  writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
290  U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
291  /* IRQ in n * cycles */
292  writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
293  /*
294  * We run one shot per tick here! (This is necessary to reconfigure,
295  * the timer will tilt if you don't!)
296  */
297  writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
298  U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
299  /* Enable timer interrupts */
300  writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
301  U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
302  /* Then enable the OS timer again */
303  writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
304  U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
305  return 0;
306 }
307 
308 
309 /* Use general purpose timer 1 as clock event */
310 static struct clock_event_device clockevent_u300_1mhz = {
311  .name = "GPT1",
312  .rating = 300, /* Reasonably fast and accurate clock event */
313  .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
314  .set_next_event = u300_set_next_event,
315  .set_mode = u300_set_mode,
316 };
317 
318 /* Clock event timer interrupt handler */
319 static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
320 {
321  struct clock_event_device *evt = &clockevent_u300_1mhz;
322  /* ACK/Clear timer IRQ for the APP GPT1 Timer */
323  writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
324  U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA);
325  evt->event_handler(evt);
326  return IRQ_HANDLED;
327 }
328 
329 static struct irqaction u300_timer_irq = {
330  .name = "U300 Timer Tick",
331  .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
332  .handler = u300_timer_interrupt,
333 };
334 
335 /*
336  * Override the global weak sched_clock symbol with this
337  * local implementation which uses the clocksource to get some
338  * better resolution when scheduling the kernel. We accept that
339  * this wraps around for now, since it is just a relative time
340  * stamp. (Inspired by OMAP implementation.)
341  */
342 
343 static u32 notrace u300_read_sched_clock(void)
344 {
345  return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
346 }
347 
348 
349 /*
350  * This sets up the system timers, clock source and clock event.
351  */
352 static void __init u300_timer_init(void)
353 {
354  struct clk *clk;
355  unsigned long rate;
356 
357  /* Clock the interrupt controller */
358  clk = clk_get_sys("apptimer", NULL);
359  BUG_ON(IS_ERR(clk));
360  clk_prepare_enable(clk);
361  rate = clk_get_rate(clk);
362 
363  setup_sched_clock(u300_read_sched_clock, 32, rate);
364 
365  /*
366  * Disable the "OS" and "DD" timers - these are designed for Symbian!
367  * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
368  */
369  writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
370  U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
371  writel(U300_TIMER_APP_ROST_TIMER_RESET,
372  U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
373  writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
374  U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
375  writel(U300_TIMER_APP_RDDT_TIMER_RESET,
376  U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
377  writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
378  U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
379 
380  /* Reset the General Purpose timer 1. */
381  writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
382  U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
383 
384  /* Set up the IRQ handler */
385  setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
386 
387  /* Reset the General Purpose timer 2 */
388  writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
389  U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
390  /* Set this timer to run around forever */
391  writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
392  /* Set continuous mode so it wraps around */
393  writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
394  U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
395  /* Disable timer interrupts */
396  writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
397  U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
398  /* Then enable the GP2 timer to use as a free running us counter */
399  writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
400  U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
401 
402  /* Use general purpose timer 2 as clock source */
403  if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC,
404  "GPT2", rate, 300, 32, clocksource_mmio_readl_up))
405  pr_err("timer: failed to initialize U300 clock source\n");
406 
407  /* Configure and register the clockevent */
408  clockevents_config_and_register(&clockevent_u300_1mhz, rate,
409  1, 0xffffffff);
410 
411  /*
412  * TODO: init and register the rest of the timers too, they can be
413  * used by hrtimers!
414  */
415 }
416 
417 /*
418  * Very simple system timer that only register the clock event and
419  * clock source.
420  */
421 struct sys_timer u300_timer = {
422  .init = u300_timer_init,
423 };
Generated on Thu Jan 10 2013 12:59:37 for Linux Kernel by   doxygen 1.8.2