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io.h
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1 #ifndef __ASM_AVR32_IO_H
2 #define __ASM_AVR32_IO_H
3 
4 #include <linux/bug.h>
5 #include <linux/kernel.h>
6 #include <linux/string.h>
7 #include <linux/types.h>
8 
9 #include <asm/addrspace.h>
10 #include <asm/byteorder.h>
11 
12 #include <mach/io.h>
13 
14 /* virt_to_phys will only work when address is in P1 or P2 */
15 static __inline__ unsigned long virt_to_phys(volatile void *address)
16 {
17  return PHYSADDR(address);
18 }
19 
20 static __inline__ void * phys_to_virt(unsigned long address)
21 {
22  return (void *)P1SEGADDR(address);
23 }
24 
25 #define cached_to_phys(addr) ((unsigned long)PHYSADDR(addr))
26 #define uncached_to_phys(addr) ((unsigned long)PHYSADDR(addr))
27 #define phys_to_cached(addr) ((void *)P1SEGADDR(addr))
28 #define phys_to_uncached(addr) ((void *)P2SEGADDR(addr))
29 
30 /*
31  * Generic IO read/write. These perform native-endian accesses. Note
32  * that some architectures will want to re-define __raw_{read,write}w.
33  */
34 extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
35 extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
36 extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
37 
38 extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
39 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
40 extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
41 
42 static inline void __raw_writeb(u8 v, volatile void __iomem *addr)
43 {
44  *(volatile u8 __force *)addr = v;
45 }
46 static inline void __raw_writew(u16 v, volatile void __iomem *addr)
47 {
48  *(volatile u16 __force *)addr = v;
49 }
50 static inline void __raw_writel(u32 v, volatile void __iomem *addr)
51 {
52  *(volatile u32 __force *)addr = v;
53 }
54 
55 static inline u8 __raw_readb(const volatile void __iomem *addr)
56 {
57  return *(const volatile u8 __force *)addr;
58 }
59 static inline u16 __raw_readw(const volatile void __iomem *addr)
60 {
61  return *(const volatile u16 __force *)addr;
62 }
63 static inline u32 __raw_readl(const volatile void __iomem *addr)
64 {
65  return *(const volatile u32 __force *)addr;
66 }
67 
68 /* Convert I/O port address to virtual address */
69 #ifndef __io
70 # define __io(p) ((void *)phys_to_uncached(p))
71 #endif
72 
73 /*
74  * Not really sure about the best way to slow down I/O on
75  * AVR32. Defining it as a no-op until we have an actual test case.
76  */
77 #define SLOW_DOWN_IO do { } while (0)
78 
79 #define __BUILD_MEMORY_SINGLE(pfx, bwl, type) \
80 static inline void \
81 pfx##write##bwl(type val, volatile void __iomem *addr) \
82 { \
83  volatile type *__addr; \
84  type __val; \
85  \
86  __addr = (void *)__swizzle_addr_##bwl((unsigned long)(addr)); \
87  __val = pfx##ioswab##bwl(__addr, val); \
88  \
89  BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
90  \
91  *__addr = __val; \
92 } \
93  \
94 static inline type pfx##read##bwl(const volatile void __iomem *addr) \
95 { \
96  volatile type *__addr; \
97  type __val; \
98  \
99  __addr = (void *)__swizzle_addr_##bwl((unsigned long)(addr)); \
100  \
101  BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
102  \
103  __val = *__addr; \
104  return pfx##ioswab##bwl(__addr, __val); \
105 }
106 
107 #define __BUILD_IOPORT_SINGLE(pfx, bwl, type, p, slow) \
108 static inline void pfx##out##bwl##p(type val, unsigned long port) \
109 { \
110  volatile type *__addr; \
111  type __val; \
112  \
113  __addr = __io(__swizzle_addr_##bwl(port)); \
114  __val = pfx##ioswab##bwl(__addr, val); \
115  \
116  BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
117  \
118  *__addr = __val; \
119  slow; \
120 } \
121  \
122 static inline type pfx##in##bwl##p(unsigned long port) \
123 { \
124  volatile type *__addr; \
125  type __val; \
126  \
127  __addr = __io(__swizzle_addr_##bwl(port)); \
128  \
129  BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
130  \
131  __val = *__addr; \
132  slow; \
133  \
134  return pfx##ioswab##bwl(__addr, __val); \
135 }
136 
137 #define __BUILD_MEMORY_PFX(bus, bwl, type) \
138  __BUILD_MEMORY_SINGLE(bus, bwl, type)
139 
140 #define BUILDIO_MEM(bwl, type) \
141  __BUILD_MEMORY_PFX(, bwl, type) \
142  __BUILD_MEMORY_PFX(__mem_, bwl, type)
143 
144 #define __BUILD_IOPORT_PFX(bus, bwl, type) \
145  __BUILD_IOPORT_SINGLE(bus, bwl, type, ,) \
146  __BUILD_IOPORT_SINGLE(bus, bwl, type, _p, SLOW_DOWN_IO)
147 
148 #define BUILDIO_IOPORT(bwl, type) \
149  __BUILD_IOPORT_PFX(, bwl, type) \
150  __BUILD_IOPORT_PFX(__mem_, bwl, type)
151 
152 BUILDIO_MEM(b, u8)
153 BUILDIO_MEM(w, u16)
154 BUILDIO_MEM(l, u32)
155 
156 BUILDIO_IOPORT(b, u8)
157 BUILDIO_IOPORT(w, u16)
158 BUILDIO_IOPORT(l, u32)
159 
160 #define readb_relaxed readb
161 #define readw_relaxed readw
162 #define readl_relaxed readl
163 
164 #define readb_be __raw_readb
165 #define readw_be __raw_readw
166 #define readl_be __raw_readl
167 
168 #define writeb_be __raw_writeb
169 #define writew_be __raw_writew
170 #define writel_be __raw_writel
171 
172 #define __BUILD_MEMORY_STRING(bwl, type) \
173 static inline void writes##bwl(volatile void __iomem *addr, \
174  const void *data, unsigned int count) \
175 { \
176  const type *__data = data; \
177  \
178  while (count--) \
179  __mem_write##bwl(*__data++, addr); \
180 } \
181  \
182 static inline void reads##bwl(const volatile void __iomem *addr, \
183  void *data, unsigned int count) \
184 { \
185  type *__data = data; \
186  \
187  while (count--) \
188  *__data++ = __mem_read##bwl(addr); \
189 }
190 
191 #define __BUILD_IOPORT_STRING(bwl, type) \
192 static inline void outs##bwl(unsigned long port, const void *data, \
193  unsigned int count) \
194 { \
195  const type *__data = data; \
196  \
197  while (count--) \
198  __mem_out##bwl(*__data++, port); \
199 } \
200  \
201 static inline void ins##bwl(unsigned long port, void *data, \
202  unsigned int count) \
203 { \
204  type *__data = data; \
205  \
206  while (count--) \
207  *__data++ = __mem_in##bwl(port); \
208 }
209 
210 #define BUILDSTRING(bwl, type) \
211  __BUILD_MEMORY_STRING(bwl, type) \
212  __BUILD_IOPORT_STRING(bwl, type)
213 
214 BUILDSTRING(b, u8)
215 BUILDSTRING(w, u16)
216 BUILDSTRING(l, u32)
217 
218 /*
219  * io{read,write}{8,16,32} macros in both le (for PCI style consumers) and native be
220  */
221 #ifndef ioread8
222 
223 #define ioread8(p) ((unsigned int)readb(p))
224 
225 #define ioread16(p) ((unsigned int)readw(p))
226 #define ioread16be(p) ((unsigned int)__raw_readw(p))
227 
228 #define ioread32(p) ((unsigned int)readl(p))
229 #define ioread32be(p) ((unsigned int)__raw_readl(p))
230 
231 #define iowrite8(v,p) writeb(v, p)
232 
233 #define iowrite16(v,p) writew(v, p)
234 #define iowrite16be(v,p) __raw_writew(v, p)
235 
236 #define iowrite32(v,p) writel(v, p)
237 #define iowrite32be(v,p) __raw_writel(v, p)
238 
239 #define ioread8_rep(p,d,c) readsb(p,d,c)
240 #define ioread16_rep(p,d,c) readsw(p,d,c)
241 #define ioread32_rep(p,d,c) readsl(p,d,c)
242 
243 #define iowrite8_rep(p,s,c) writesb(p,s,c)
244 #define iowrite16_rep(p,s,c) writesw(p,s,c)
245 #define iowrite32_rep(p,s,c) writesl(p,s,c)
246 
247 #endif
248 
249 static inline void memcpy_fromio(void * to, const volatile void __iomem *from,
250  unsigned long count)
251 {
252  memcpy(to, (const void __force *)from, count);
253 }
254 
255 static inline void memcpy_toio(volatile void __iomem *to, const void * from,
256  unsigned long count)
257 {
258  memcpy((void __force *)to, from, count);
259 }
260 
261 static inline void memset_io(volatile void __iomem *addr, unsigned char val,
262  unsigned long count)
263 {
264  memset((void __force *)addr, val, count);
265 }
266 
267 #define mmiowb()
268 
269 #define IO_SPACE_LIMIT 0xffffffff
270 
271 extern void __iomem *__ioremap(unsigned long offset, size_t size,
272  unsigned long flags);
273 extern void __iounmap(void __iomem *addr);
274 
275 /*
276  * ioremap - map bus memory into CPU space
277  * @offset bus address of the memory
278  * @size size of the resource to map
279  *
280  * ioremap performs a platform specific sequence of operations to make
281  * bus memory CPU accessible via the readb/.../writel functions and
282  * the other mmio helpers. The returned address is not guaranteed to
283  * be usable directly as a virtual address.
284  */
285 #define ioremap(offset, size) \
286  __ioremap((offset), (size), 0)
287 
288 #define ioremap_nocache(offset, size) \
289  __ioremap((offset), (size), 0)
290 
291 #define iounmap(addr) \
292  __iounmap(addr)
293 
294 #define cached(addr) P1SEGADDR(addr)
295 #define uncached(addr) P2SEGADDR(addr)
296 
297 #define virt_to_bus virt_to_phys
298 #define bus_to_virt phys_to_virt
299 #define page_to_bus page_to_phys
300 #define bus_to_page phys_to_page
301 
302 /*
303  * Create a virtual mapping cookie for an IO port range. There exists
304  * no such thing as port-based I/O on AVR32, so a regular ioremap()
305  * should do what we need.
306  */
307 #define ioport_map(port, nr) ioremap(port, nr)
308 #define ioport_unmap(port) iounmap(port)
309 
310 /*
311  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
312  * access
313  */
314 #define xlate_dev_mem_ptr(p) __va(p)
315 
316 /*
317  * Convert a virtual cached pointer to an uncached pointer
318  */
319 #define xlate_dev_kmem_ptr(p) p
320 
321 #endif /* __ASM_AVR32_IO_H */
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