Macros
#define	CH_SPORT0_TX 0

#define	CH_SPORT0_RX 1

#define	CH_SPORT1_TX 2

#define	CH_SPORT1_RX 3

#define	CH_SPORT2_TX 4

#define	CH_SPORT2_RX 5

#define	CH_SPI0_TX 6

#define	CH_SPI0_RX 7

#define	CH_SPI1_TX 8

#define	CH_SPI1_RX 9

#define	CH_RSI 10

#define	CH_SDU 11

#define	CH_LP0 13

#define	CH_LP1 14

#define	CH_LP2 15

#define	CH_LP3 16

#define	CH_UART0_TX 17

#define	CH_UART0_RX 18

#define	CH_UART1_TX 19

#define	CH_UART1_RX 20

#define	CH_MEM_STREAM0_SRC_CRC0 21

#define	CH_MEM_STREAM0_SRC CH_MEM_STREAM0_SRC_CRC0

#define	CH_MEM_STREAM0_DEST_CRC0 22

#define	CH_MEM_STREAM0_DEST CH_MEM_STREAM0_DEST_CRC0

#define	CH_MEM_STREAM1_SRC_CRC1 23

#define	CH_MEM_STREAM1_SRC CH_MEM_STREAM1_SRC_CRC1

#define	CH_MEM_STREAM1_DEST_CRC1 24

#define	CH_MEM_STREAM1_DEST CH_MEM_STREAM1_DEST_CRC1

#define	CH_MEM_STREAM2_SRC 25

#define	CH_MEM_STREAM2_DEST 26

#define	CH_MEM_STREAM3_SRC 27

#define	CH_MEM_STREAM3_DEST 28

#define	CH_EPPI0_CH0 29

#define	CH_EPPI0_CH1 30

#define	CH_EPPI1_CH0 31

#define	CH_EPPI1_CH1 32

#define	CH_EPPI2_CH0 33

#define	CH_EPPI2_CH1 34

#define	CH_PIXC_CH0 35

#define	CH_PIXC_CH1 36

#define	CH_PIXC_CH2 37

#define	CH_PVP_CPDOB 38

#define	CH_PVP_CPDOC 39

#define	CH_PVP_CPSTAT 40

#define	CH_PVP_CPCI 41

#define	CH_PVP_MPDO 42

#define	CH_PVP_MPDI 43

#define	CH_PVP_MPSTAT 44

#define	CH_PVP_MPCI 45

#define	CH_PVP_CPDOA 46

#define	MAX_DMA_CHANNELS 47

#define	MAX_DMA_SUSPEND_CHANNELS 0

#define	DMA_MMR_SIZE_32

#define	bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_SRC_CRC0_CONFIG

#define	bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_SRC_CRC0_CONFIG

#define	bfin_read_MDMA_S0_IRQ_STATUS bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS

#define	bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS

#define	bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_SRC_CRC0_START_ADDR

#define	bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_SRC_CRC0_X_COUNT

#define	bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_SRC_CRC0_X_MODIFY

#define	bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_SRC_CRC0_Y_COUNT

#define	bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_SRC_CRC0_Y_MODIFY

#define	bfin_read_MDMA_D0_CONFIG bfin_read_MDMA0_DEST_CRC0_CONFIG

#define	bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_DEST_CRC0_CONFIG

#define	bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS

#define	bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS

#define	bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_DEST_CRC0_START_ADDR

#define	bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_DEST_CRC0_X_COUNT

#define	bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_DEST_CRC0_X_MODIFY

#define	bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_DEST_CRC0_Y_COUNT

#define	bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_DEST_CRC0_Y_MODIFY

#define	bfin_read_MDMA_S1_CONFIG bfin_read_MDMA1_SRC_CRC1_CONFIG

#define	bfin_write_MDMA_S1_CONFIG bfin_write_MDMA1_SRC_CRC1_CONFIG

#define	bfin_read_MDMA_D1_CONFIG bfin_read_MDMA1_DEST_CRC1_CONFIG

#define	bfin_write_MDMA_D1_CONFIG bfin_write_MDMA1_DEST_CRC1_CONFIG

#define	bfin_read_MDMA_D1_IRQ_STATUS bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS

#define	bfin_write_MDMA_D1_IRQ_STATUS bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS

#define	bfin_read_MDMA_S3_CONFIG bfin_read_MDMA3_SRC_CONFIG

#define	bfin_write_MDMA_S3_CONFIG bfin_write_MDMA3_SRC_CONFIG

#define	bfin_read_MDMA_S3_IRQ_STATUS bfin_read_MDMA3_SRC_IRQ_STATUS

#define	bfin_write_MDMA_S3_IRQ_STATUS bfin_write_MDMA3_SRC_IRQ_STATUS

#define	bfin_write_MDMA_S3_START_ADDR bfin_write_MDMA3_SRC_START_ADDR

#define	bfin_write_MDMA_S3_X_COUNT bfin_write_MDMA3_SRC_X_COUNT

#define	bfin_write_MDMA_S3_X_MODIFY bfin_write_MDMA3_SRC_X_MODIFY

#define	bfin_write_MDMA_S3_Y_COUNT bfin_write_MDMA3_SRC_Y_COUNT

#define	bfin_write_MDMA_S3_Y_MODIFY bfin_write_MDMA3_SRC_Y_MODIFY

#define	bfin_read_MDMA_D3_CONFIG bfin_read_MDMA3_DEST_CONFIG

#define	bfin_write_MDMA_D3_CONFIG bfin_write_MDMA3_DEST_CONFIG

#define	bfin_read_MDMA_D3_IRQ_STATUS bfin_read_MDMA3_DEST_IRQ_STATUS

#define	bfin_write_MDMA_D3_IRQ_STATUS bfin_write_MDMA3_DEST_IRQ_STATUS

#define	bfin_write_MDMA_D3_START_ADDR bfin_write_MDMA3_DEST_START_ADDR

#define	bfin_write_MDMA_D3_X_COUNT bfin_write_MDMA3_DEST_X_COUNT

#define	bfin_write_MDMA_D3_X_MODIFY bfin_write_MDMA3_DEST_X_MODIFY

#define	bfin_write_MDMA_D3_Y_COUNT bfin_write_MDMA3_DEST_Y_COUNT

#define	bfin_write_MDMA_D3_Y_MODIFY bfin_write_MDMA3_DEST_Y_MODIFY

#define	MDMA_S0_NEXT_DESC_PTR MDMA0_SRC_CRC0_NEXT_DESC_PTR

#define	MDMA_D0_NEXT_DESC_PTR MDMA0_DEST_CRC0_NEXT_DESC_PTR

#define	MDMA_S1_NEXT_DESC_PTR MDMA1_SRC_CRC1_NEXT_DESC_PTR

#define	MDMA_D1_NEXT_DESC_PTR MDMA1_DEST_CRC1_NEXT_DESC_PTR

Macro Definition Documentation

#define bfin_read_MDMA_D0_CONFIG bfin_read_MDMA0_DEST_CRC0_CONFIG

Definition at line 75 of file dma.h.

#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS

Definition at line 77 of file dma.h.

#define bfin_read_MDMA_D1_CONFIG bfin_read_MDMA1_DEST_CRC1_CONFIG

Definition at line 87 of file dma.h.

#define bfin_read_MDMA_D1_IRQ_STATUS bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS

Definition at line 89 of file dma.h.

#define bfin_read_MDMA_D3_CONFIG bfin_read_MDMA3_DEST_CONFIG

Definition at line 101 of file dma.h.

#define bfin_read_MDMA_D3_IRQ_STATUS bfin_read_MDMA3_DEST_IRQ_STATUS

Definition at line 103 of file dma.h.

#define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_SRC_CRC0_CONFIG

Definition at line 66 of file dma.h.

#define bfin_read_MDMA_S0_IRQ_STATUS bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS

Definition at line 68 of file dma.h.

#define bfin_read_MDMA_S1_CONFIG bfin_read_MDMA1_SRC_CRC1_CONFIG

Definition at line 85 of file dma.h.

#define bfin_read_MDMA_S3_CONFIG bfin_read_MDMA3_SRC_CONFIG

Definition at line 92 of file dma.h.

#define bfin_read_MDMA_S3_IRQ_STATUS bfin_read_MDMA3_SRC_IRQ_STATUS

Definition at line 94 of file dma.h.

#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_DEST_CRC0_CONFIG

Definition at line 76 of file dma.h.

#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS

Definition at line 78 of file dma.h.

#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_DEST_CRC0_START_ADDR

Definition at line 79 of file dma.h.

#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_DEST_CRC0_X_COUNT

Definition at line 80 of file dma.h.

#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_DEST_CRC0_X_MODIFY

Definition at line 81 of file dma.h.

#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_DEST_CRC0_Y_COUNT

Definition at line 82 of file dma.h.

#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_DEST_CRC0_Y_MODIFY

Definition at line 83 of file dma.h.

#define bfin_write_MDMA_D1_CONFIG bfin_write_MDMA1_DEST_CRC1_CONFIG

Definition at line 88 of file dma.h.

#define bfin_write_MDMA_D1_IRQ_STATUS bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS

Definition at line 90 of file dma.h.

#define bfin_write_MDMA_D3_CONFIG bfin_write_MDMA3_DEST_CONFIG

Definition at line 102 of file dma.h.

#define bfin_write_MDMA_D3_IRQ_STATUS bfin_write_MDMA3_DEST_IRQ_STATUS

Definition at line 104 of file dma.h.

#define bfin_write_MDMA_D3_START_ADDR bfin_write_MDMA3_DEST_START_ADDR

Definition at line 105 of file dma.h.

#define bfin_write_MDMA_D3_X_COUNT bfin_write_MDMA3_DEST_X_COUNT

Definition at line 106 of file dma.h.

#define bfin_write_MDMA_D3_X_MODIFY bfin_write_MDMA3_DEST_X_MODIFY

Definition at line 107 of file dma.h.

#define bfin_write_MDMA_D3_Y_COUNT bfin_write_MDMA3_DEST_Y_COUNT

Definition at line 108 of file dma.h.

#define bfin_write_MDMA_D3_Y_MODIFY bfin_write_MDMA3_DEST_Y_MODIFY

Definition at line 109 of file dma.h.

#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_SRC_CRC0_CONFIG

Definition at line 67 of file dma.h.

#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS

Definition at line 69 of file dma.h.

#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_SRC_CRC0_START_ADDR

Definition at line 70 of file dma.h.

#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_SRC_CRC0_X_COUNT

Definition at line 71 of file dma.h.

#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_SRC_CRC0_X_MODIFY

Definition at line 72 of file dma.h.

#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_SRC_CRC0_Y_COUNT

Definition at line 73 of file dma.h.

#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_SRC_CRC0_Y_MODIFY

Definition at line 74 of file dma.h.

#define bfin_write_MDMA_S1_CONFIG bfin_write_MDMA1_SRC_CRC1_CONFIG

Definition at line 86 of file dma.h.

#define bfin_write_MDMA_S3_CONFIG bfin_write_MDMA3_SRC_CONFIG

Definition at line 93 of file dma.h.

#define bfin_write_MDMA_S3_IRQ_STATUS bfin_write_MDMA3_SRC_IRQ_STATUS

Definition at line 95 of file dma.h.

#define bfin_write_MDMA_S3_START_ADDR bfin_write_MDMA3_SRC_START_ADDR

Definition at line 96 of file dma.h.

#define bfin_write_MDMA_S3_X_COUNT bfin_write_MDMA3_SRC_X_COUNT

Definition at line 97 of file dma.h.

#define bfin_write_MDMA_S3_X_MODIFY bfin_write_MDMA3_SRC_X_MODIFY

Definition at line 98 of file dma.h.

#define bfin_write_MDMA_S3_Y_COUNT bfin_write_MDMA3_SRC_Y_COUNT

Definition at line 99 of file dma.h.

#define bfin_write_MDMA_S3_Y_MODIFY bfin_write_MDMA3_SRC_Y_MODIFY

Definition at line 100 of file dma.h.

#define CH_EPPI0_CH0 29

Definition at line 43 of file dma.h.

#define CH_EPPI0_CH1 30

Definition at line 44 of file dma.h.

#define CH_EPPI1_CH0 31

Definition at line 45 of file dma.h.

#define CH_EPPI1_CH1 32

Definition at line 46 of file dma.h.

#define CH_EPPI2_CH0 33

Definition at line 47 of file dma.h.

#define CH_EPPI2_CH1 34

Definition at line 48 of file dma.h.

#define CH_LP0 13

Definition at line 23 of file dma.h.

#define CH_LP1 14

Definition at line 24 of file dma.h.

#define CH_LP2 15

Definition at line 25 of file dma.h.

#define CH_LP3 16

Definition at line 26 of file dma.h.

#define CH_MEM_STREAM0_DEST CH_MEM_STREAM0_DEST_CRC0

Definition at line 34 of file dma.h.

#define CH_MEM_STREAM0_DEST_CRC0 22

Definition at line 33 of file dma.h.

#define CH_MEM_STREAM0_SRC CH_MEM_STREAM0_SRC_CRC0

Definition at line 32 of file dma.h.

#define CH_MEM_STREAM0_SRC_CRC0 21

Definition at line 31 of file dma.h.

#define CH_MEM_STREAM1_DEST CH_MEM_STREAM1_DEST_CRC1

Definition at line 38 of file dma.h.

#define CH_MEM_STREAM1_DEST_CRC1 24

Definition at line 37 of file dma.h.

#define CH_MEM_STREAM1_SRC CH_MEM_STREAM1_SRC_CRC1

Definition at line 36 of file dma.h.

#define CH_MEM_STREAM1_SRC_CRC1 23

Definition at line 35 of file dma.h.

#define CH_MEM_STREAM2_DEST 26

Definition at line 40 of file dma.h.

#define CH_MEM_STREAM2_SRC 25

Definition at line 39 of file dma.h.

#define CH_MEM_STREAM3_DEST 28

Definition at line 42 of file dma.h.

#define CH_MEM_STREAM3_SRC 27

Definition at line 41 of file dma.h.

#define CH_PIXC_CH0 35

Definition at line 49 of file dma.h.

#define CH_PIXC_CH1 36

Definition at line 50 of file dma.h.

#define CH_PIXC_CH2 37

Definition at line 51 of file dma.h.

#define CH_PVP_CPCI 41

Definition at line 55 of file dma.h.

#define CH_PVP_CPDOA 46

Definition at line 60 of file dma.h.

#define CH_PVP_CPDOB 38

Definition at line 52 of file dma.h.

#define CH_PVP_CPDOC 39

Definition at line 53 of file dma.h.

#define CH_PVP_CPSTAT 40

Definition at line 54 of file dma.h.

#define CH_PVP_MPCI 45

Definition at line 59 of file dma.h.

#define CH_PVP_MPDI 43

Definition at line 57 of file dma.h.

#define CH_PVP_MPDO 42

Definition at line 56 of file dma.h.

#define CH_PVP_MPSTAT 44

Definition at line 58 of file dma.h.

#define CH_RSI 10

Definition at line 21 of file dma.h.

#define CH_SDU 11

Definition at line 22 of file dma.h.

#define CH_SPI0_RX 7

Definition at line 18 of file dma.h.

#define CH_SPI0_TX 6

Definition at line 17 of file dma.h.

#define CH_SPI1_RX 9

Definition at line 20 of file dma.h.

#define CH_SPI1_TX 8

Definition at line 19 of file dma.h.

#define CH_SPORT0_RX 1

Definition at line 12 of file dma.h.

#define CH_SPORT0_TX 0

Definition at line 11 of file dma.h.

#define CH_SPORT1_RX 3

Definition at line 14 of file dma.h.

#define CH_SPORT1_TX 2

Definition at line 13 of file dma.h.

#define CH_SPORT2_RX 5

Definition at line 16 of file dma.h.

#define CH_SPORT2_TX 4

Definition at line 15 of file dma.h.

#define CH_UART0_RX 18

Definition at line 28 of file dma.h.

#define CH_UART0_TX 17

Definition at line 27 of file dma.h.

#define CH_UART1_RX 20

Definition at line 30 of file dma.h.

#define CH_UART1_TX 19

Definition at line 29 of file dma.h.

#define DMA_MMR_SIZE_32

Definition at line 64 of file dma.h.

#define MAX_DMA_CHANNELS 47

Definition at line 62 of file dma.h.

#define MAX_DMA_SUSPEND_CHANNELS 0

Definition at line 63 of file dma.h.

#define MDMA_D0_NEXT_DESC_PTR MDMA0_DEST_CRC0_NEXT_DESC_PTR

Definition at line 112 of file dma.h.

#define MDMA_D1_NEXT_DESC_PTR MDMA1_DEST_CRC1_NEXT_DESC_PTR

Definition at line 114 of file dma.h.

#define MDMA_S0_NEXT_DESC_PTR MDMA0_SRC_CRC0_NEXT_DESC_PTR

Definition at line 111 of file dma.h.

#define MDMA_S1_NEXT_DESC_PTR MDMA1_SRC_CRC1_NEXT_DESC_PTR

Definition at line 113 of file dma.h.

Macros

Macro Definition Documentation