Go to the documentation of this file. 1 #ifndef __iop_sap_in_defs_h
2 #define __iop_sap_in_defs_h
18 #define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
24 #define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
44 #define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
49 #define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
53 #ifndef REG_RD_INT_VECT
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
66 #define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
71 #define reg_page_size 8192
75 #define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
89 unsigned int byte0_sel : 2;
90 unsigned int byte0_ext_src : 3;
91 unsigned int byte0_edge : 2;
92 unsigned int byte0_delay : 1;
93 unsigned int byte1_sel : 2;
94 unsigned int byte1_ext_src : 3;
95 unsigned int byte1_edge : 2;
96 unsigned int byte1_delay : 1;
97 unsigned int byte2_sel : 2;
98 unsigned int byte2_ext_src : 3;
99 unsigned int byte2_edge : 2;
100 unsigned int byte2_delay : 1;
101 unsigned int byte3_sel : 2;
102 unsigned int byte3_ext_src : 3;
103 unsigned int byte3_edge : 2;
104 unsigned int byte3_delay : 1;
106 #define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0
107 #define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0
111 unsigned int byte0_sel : 2;
112 unsigned int byte0_ext_src : 3;
113 unsigned int byte0_edge : 2;
114 unsigned int byte0_delay : 1;
115 unsigned int byte1_sel : 2;
116 unsigned int byte1_ext_src : 3;
117 unsigned int byte1_edge : 2;
118 unsigned int byte1_delay : 1;
119 unsigned int byte2_sel : 2;
120 unsigned int byte2_ext_src : 3;
121 unsigned int byte2_edge : 2;
122 unsigned int byte2_delay : 1;
123 unsigned int byte3_sel : 2;
124 unsigned int byte3_ext_src : 3;
125 unsigned int byte3_edge : 2;
126 unsigned int byte3_delay : 1;
128 #define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4
129 #define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4
131 #define STRIDE_iop_sap_in_rw_gio 4
134 unsigned int sync_sel : 2;
135 unsigned int sync_ext_src : 3;
136 unsigned int sync_edge : 2;
138 unsigned int logic : 2;
139 unsigned int dummy1 : 22;
141 #define REG_RD_ADDR_iop_sap_in_rw_gio 8
142 #define REG_WR_ADDR_iop_sap_in_rw_gio 8