Go to the source code of this file.
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#define | REG_RD(scope, inst, reg) |
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#define | REG_WR(scope, inst, reg, val) |
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#define | REG_RD_VECT(scope, inst, reg, index) |
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#define | REG_WR_VECT(scope, inst, reg, index, val) |
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#define | REG_RD_INT(scope, inst, reg) REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) |
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#define | REG_WR_INT(scope, inst, reg, val) REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) |
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#define | REG_RD_INT_VECT(scope, inst, reg, index) |
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#define | REG_WR_INT_VECT(scope, inst, reg, index, val) |
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#define | REG_TYPE_CONV(type, orgtype, val) ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) |
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#define | reg_page_size 8192 |
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#define | REG_ADDR(scope, inst, reg) ( (inst) + REG_RD_ADDR_##scope##_##reg ) |
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#define | REG_ADDR_VECT(scope, inst, reg, index) |
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#define | REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0 |
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#define | REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0 |
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#define | REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4 |
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#define | REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4 |
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#define | STRIDE_iop_sap_in_rw_gio 4 |
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#define | REG_RD_ADDR_iop_sap_in_rw_gio 8 |
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#define | REG_WR_ADDR_iop_sap_in_rw_gio 8 |
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enum | {
regk_iop_sap_in_and = 0x00000002,
regk_iop_sap_in_ext_clk200 = 0x00000003,
regk_iop_sap_in_gio1 = 0x00000000,
regk_iop_sap_in_gio13 = 0x00000005,
regk_iop_sap_in_gio18 = 0x00000003,
regk_iop_sap_in_gio19 = 0x00000004,
regk_iop_sap_in_gio21 = 0x00000006,
regk_iop_sap_in_gio23 = 0x00000005,
regk_iop_sap_in_gio29 = 0x00000007,
regk_iop_sap_in_gio5 = 0x00000004,
regk_iop_sap_in_gio6 = 0x00000001,
regk_iop_sap_in_gio7 = 0x00000002,
regk_iop_sap_in_inv = 0x00000001,
regk_iop_sap_in_neg = 0x00000002,
regk_iop_sap_in_no = 0x00000000,
regk_iop_sap_in_no_del_ext_clk200 = 0x00000001,
regk_iop_sap_in_none = 0x00000000,
regk_iop_sap_in_or = 0x00000003,
regk_iop_sap_in_pos = 0x00000001,
regk_iop_sap_in_pos_neg = 0x00000003,
regk_iop_sap_in_rw_bus0_sync_default = 0x02020202,
regk_iop_sap_in_rw_bus1_sync_default = 0x02020202,
regk_iop_sap_in_rw_gio_default = 0x00000002,
regk_iop_sap_in_rw_gio_size = 0x00000020,
regk_iop_sap_in_timer_grp0_tmr3 = 0x00000006,
regk_iop_sap_in_timer_grp1_tmr3 = 0x00000004,
regk_iop_sap_in_timer_grp2_tmr3 = 0x00000005,
regk_iop_sap_in_timer_grp3_tmr3 = 0x00000007,
regk_iop_sap_in_tmr_clk200 = 0x00000000,
regk_iop_sap_in_two_clk200 = 0x00000002,
regk_iop_sap_in_yes = 0x00000001
} |
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#define reg_page_size 8192 |
#define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0 |
#define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4 |
#define REG_RD_ADDR_iop_sap_in_rw_gio 8 |
#define REG_TYPE_CONV |
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type, |
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orgtype, |
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val |
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) |
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#define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0 |
#define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4 |
#define REG_WR_ADDR_iop_sap_in_rw_gio 8 |
#define STRIDE_iop_sap_in_rw_gio 4 |
- Enumerator:
regk_iop_sap_in_and |
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regk_iop_sap_in_ext_clk200 |
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regk_iop_sap_in_gio1 |
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regk_iop_sap_in_gio13 |
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regk_iop_sap_in_gio18 |
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regk_iop_sap_in_gio19 |
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regk_iop_sap_in_gio21 |
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regk_iop_sap_in_gio23 |
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regk_iop_sap_in_gio29 |
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regk_iop_sap_in_gio5 |
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regk_iop_sap_in_gio6 |
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regk_iop_sap_in_gio7 |
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regk_iop_sap_in_inv |
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regk_iop_sap_in_neg |
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regk_iop_sap_in_no |
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regk_iop_sap_in_no_del_ext_clk200 |
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regk_iop_sap_in_none |
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regk_iop_sap_in_or |
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regk_iop_sap_in_pos |
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regk_iop_sap_in_pos_neg |
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regk_iop_sap_in_rw_bus0_sync_default |
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regk_iop_sap_in_rw_bus1_sync_default |
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regk_iop_sap_in_rw_gio_default |
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regk_iop_sap_in_rw_gio_size |
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regk_iop_sap_in_timer_grp0_tmr3 |
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regk_iop_sap_in_timer_grp1_tmr3 |
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regk_iop_sap_in_timer_grp2_tmr3 |
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regk_iop_sap_in_timer_grp3_tmr3 |
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regk_iop_sap_in_tmr_clk200 |
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regk_iop_sap_in_two_clk200 |
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regk_iop_sap_in_yes |
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Definition at line 146 of file iop_sap_in_defs.h.