Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
ioc3.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2005 Silicon Graphics, Inc.
3  */
4 #ifndef IA64_SN_IOC3_H
5 #define IA64_SN_IOC3_H
6 
7 /* serial port register map */
8 struct ioc3_serialregs {
9  uint32_t sscr;
10  uint32_t stpir;
11  uint32_t stcir;
12  uint32_t srpir;
13  uint32_t srcir;
14  uint32_t srtr;
15  uint32_t shadow;
16 };
17 
18 /* SUPERIO uart register map */
19 struct ioc3_uartregs {
20  char iu_lcr;
21  union {
22  char iir; /* read only */
23  char fcr; /* write only */
24  } u3;
25  union {
26  char ier; /* DLAB == 0 */
27  char dlm; /* DLAB == 1 */
28  } u2;
29  union {
30  char rbr; /* read only, DLAB == 0 */
31  char thr; /* write only, DLAB == 0 */
32  char dll; /* DLAB == 1 */
33  } u1;
34  char iu_scr;
35  char iu_msr;
36  char iu_lsr;
37  char iu_mcr;
38 };
39 
40 #define iu_rbr u1.rbr
41 #define iu_thr u1.thr
42 #define iu_dll u1.dll
43 #define iu_ier u2.ier
44 #define iu_dlm u2.dlm
45 #define iu_iir u3.iir
46 #define iu_fcr u3.fcr
47 
48 struct ioc3_sioregs {
49  char fill[0x170];
50  struct ioc3_uartregs uartb;
51  struct ioc3_uartregs uarta;
52 };
53 
54 /* PCI IO/mem space register map */
55 struct ioc3 {
56  uint32_t pci_id;
57  uint32_t pci_scr;
58  uint32_t pci_rev;
59  uint32_t pci_lat;
60  uint32_t pci_addr;
61  uint32_t pci_err_addr_l;
62  uint32_t pci_err_addr_h;
63 
64  uint32_t sio_ir;
65  /* these registers are read-only for general kernel code. To
66  * modify them use the functions in ioc3.c
67  */
68  uint32_t sio_ies;
69  uint32_t sio_iec;
70  uint32_t sio_cr;
71  uint32_t int_out;
72  uint32_t mcr;
73  uint32_t gpcr_s;
74  uint32_t gpcr_c;
75  uint32_t gpdr;
76  uint32_t gppr[9];
77  char fill[0x4c];
78 
79  /* serial port registers */
80  uint32_t sbbr_h;
81  uint32_t sbbr_l;
82 
83  struct ioc3_serialregs port_a;
84  struct ioc3_serialregs port_b;
85  char fill1[0x1ff10];
86  /* superio registers */
87  struct ioc3_sioregs sregs;
88 };
89 
90 /* These don't exist on the ioc3 serial card... */
91 #define eier fill1[8]
92 #define eisr fill1[4]
93 
94 #define PCI_LAT 0xc /* Latency Timer */
95 #define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */
96 #define UARTA_BASE 0x178
97 #define UARTB_BASE 0x170
98 
99 
100 /* bitmasks for serial RX status byte */
101 #define RXSB_OVERRUN 0x01 /* char(s) lost */
102 #define RXSB_PAR_ERR 0x02 /* parity error */
103 #define RXSB_FRAME_ERR 0x04 /* framing error */
104 #define RXSB_BREAK 0x08 /* break character */
105 #define RXSB_CTS 0x10 /* state of CTS */
106 #define RXSB_DCD 0x20 /* state of DCD */
107 #define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */
108 #define RXSB_DATA_VALID 0x80 /* FRAME_ERR PAR_ERR & BREAK valid */
109 
110 /* bitmasks for serial TX control byte */
111 #define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */
112 #define TXCB_INVALID 0x00 /* byte is invalid */
113 #define TXCB_VALID 0x40 /* byte is valid */
114 #define TXCB_MCR 0x80 /* data<7:0> to modem cntrl register */
115 #define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */
116 
117 /* bitmasks for SBBR_L */
118 #define SBBR_L_SIZE 0x00000001 /* 0 1KB rings, 1 4KB rings */
119 
120 /* bitmasks for SSCR_<A:B> */
121 #define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */
122 #define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
123 #define SSCR_HFC_EN 0x00020000 /* h/w flow cntrl enabled */
124 #define SSCR_RX_RING_DCD 0x00040000 /* postRX record on delta-DCD */
125 #define SSCR_RX_RING_CTS 0x00080000 /* postRX record on delta-CTS */
126 #define SSCR_HIGH_SPD 0x00100000 /* 4X speed */
127 #define SSCR_DIAG 0x00200000 /* bypass clock divider */
128 #define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */
129 #define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */
130 #define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */
131 #define SSCR_PAUSE_STATE 0x40000000 /* set when PAUSE takes effect*/
132 #define SSCR_RESET 0x80000000 /* reset DMA channels */
133 
134 /* all producer/comsumer pointers are the same bitfield */
135 #define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */
136 #define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */
137 #define PROD_CONS_PTR_OFF 3
138 
139 /* bitmasks for SRCIR_<A:B> */
140 #define SRCIR_ARM 0x80000000 /* arm RX timer */
141 
142 /* bitmasks for SHADOW_<A:B> */
143 #define SHADOW_DR 0x00000001 /* data ready */
144 #define SHADOW_OE 0x00000002 /* overrun error */
145 #define SHADOW_PE 0x00000004 /* parity error */
146 #define SHADOW_FE 0x00000008 /* framing error */
147 #define SHADOW_BI 0x00000010 /* break interrupt */
148 #define SHADOW_THRE 0x00000020 /* transmit holding reg empty */
149 #define SHADOW_TEMT 0x00000040 /* transmit shift reg empty */
150 #define SHADOW_RFCE 0x00000080 /* char in RX fifo has error */
151 #define SHADOW_DCTS 0x00010000 /* delta clear to send */
152 #define SHADOW_DDCD 0x00080000 /* delta data carrier detect */
153 #define SHADOW_CTS 0x00100000 /* clear to send */
154 #define SHADOW_DCD 0x00800000 /* data carrier detect */
155 #define SHADOW_DTR 0x01000000 /* data terminal ready */
156 #define SHADOW_RTS 0x02000000 /* request to send */
157 #define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
158 #define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
159 #define SHADOW_LOOP 0x10000000 /* loopback enabled */
160 
161 /* bitmasks for SRTR_<A:B> */
162 #define SRTR_CNT 0x00000fff /* reload value for RX timer */
163 #define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */
164 #define SRTR_CNT_VAL_SHIFT 16
165 #define SRTR_HZ 16000 /* SRTR clock frequency */
166 
167 /* bitmasks for SIO_IR, SIO_IEC and SIO_IES */
168 #define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */
169 #define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */
170 #define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */
171 #define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */
172 #define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */
173 #define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */
174 #define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */
175 #define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */
176 #define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */
177 #define SIO_IR_SB_TX_MT 0x00000200
178 #define SIO_IR_SB_RX_FULL 0x00000400
179 #define SIO_IR_SB_RX_HIGH 0x00000800
180 #define SIO_IR_SB_RX_TIMER 0x00001000
181 #define SIO_IR_SB_DELTA_DCD 0x00002000
182 #define SIO_IR_SB_DELTA_CTS 0x00004000
183 #define SIO_IR_SB_INT 0x00008000
184 #define SIO_IR_SB_TX_EXPLICIT 0x00010000
185 #define SIO_IR_SB_MEMERR 0x00020000
186 #define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */
187 #define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */
188 #define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */
189 #define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */
190 #define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */
191 #define SIO_IR_RT_INT 0x08000000 /* RT output pulse */
192 #define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */
193 #define SIO_IR_GEN_INT_SHIFT 28
194 
195 /* per device interrupt masks */
196 #define SIO_IR_SA (SIO_IR_SA_TX_MT | \
197  SIO_IR_SA_RX_FULL | \
198  SIO_IR_SA_RX_HIGH | \
199  SIO_IR_SA_RX_TIMER | \
200  SIO_IR_SA_DELTA_DCD | \
201  SIO_IR_SA_DELTA_CTS | \
202  SIO_IR_SA_INT | \
203  SIO_IR_SA_TX_EXPLICIT | \
204  SIO_IR_SA_MEMERR)
205 
206 #define SIO_IR_SB (SIO_IR_SB_TX_MT | \
207  SIO_IR_SB_RX_FULL | \
208  SIO_IR_SB_RX_HIGH | \
209  SIO_IR_SB_RX_TIMER | \
210  SIO_IR_SB_DELTA_DCD | \
211  SIO_IR_SB_DELTA_CTS | \
212  SIO_IR_SB_INT | \
213  SIO_IR_SB_TX_EXPLICIT | \
214  SIO_IR_SB_MEMERR)
215 
216 #define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | \
217  SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
218 #define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
219 
220 /* bitmasks for SIO_CR */
221 #define SIO_CR_CMD_PULSE_SHIFT 15
222 #define SIO_CR_SER_A_BASE_SHIFT 1
223 #define SIO_CR_SER_B_BASE_SHIFT 8
224 #define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */
225 #define SIO_CR_ARB_DIAG_TXA 0x00000000
226 #define SIO_CR_ARB_DIAG_RXA 0x00080000
227 #define SIO_CR_ARB_DIAG_TXB 0x00100000
228 #define SIO_CR_ARB_DIAG_RXB 0x00180000
229 #define SIO_CR_ARB_DIAG_PP 0x00200000
230 #define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */
231 
232 /* defs for some of the generic I/O pins */
233 #define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */
234 #define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */
235 #define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */
236 
237 #define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */
238 #define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin cntrling uartb modeselect */
239 #define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin cntrling uarta modeselect */
240 
241 #endif /* IA64_SN_IOC3_H */
Generated on Thu Jan 10 2013 13:06:17 for Linux Kernel by   doxygen 1.8.2