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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Data Structures | |
| struct | ioc3_serialregs |
| struct | ioc3_uartregs |
| struct | ioc3_sioregs |
| struct | ioc3 |
Macros | |
| #define | iu_rbr u1.rbr |
| #define | iu_thr u1.thr |
| #define | iu_dll u1.dll |
| #define | iu_ier u2.ier |
| #define | iu_dlm u2.dlm |
| #define | iu_iir u3.iir |
| #define | iu_fcr u3.fcr |
| #define | eier fill1[8] |
| #define | eisr fill1[4] |
| #define | PCI_LAT 0xc /* Latency Timer */ |
| #define | PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */ |
| #define | UARTA_BASE 0x178 |
| #define | UARTB_BASE 0x170 |
| #define | RXSB_OVERRUN 0x01 /* char(s) lost */ |
| #define | RXSB_PAR_ERR 0x02 /* parity error */ |
| #define | RXSB_FRAME_ERR 0x04 /* framing error */ |
| #define | RXSB_BREAK 0x08 /* break character */ |
| #define | RXSB_CTS 0x10 /* state of CTS */ |
| #define | RXSB_DCD 0x20 /* state of DCD */ |
| #define | RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */ |
| #define | RXSB_DATA_VALID 0x80 /* FRAME_ERR PAR_ERR & BREAK valid */ |
| #define | TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */ |
| #define | TXCB_INVALID 0x00 /* byte is invalid */ |
| #define | TXCB_VALID 0x40 /* byte is valid */ |
| #define | TXCB_MCR 0x80 /* data<7:0> to modem cntrl register */ |
| #define | TXCB_DELAY 0xc0 /* delay data<7:0> mSec */ |
| #define | SBBR_L_SIZE 0x00000001 /* 0 1KB rings, 1 4KB rings */ |
| #define | SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */ |
| #define | SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */ |
| #define | SSCR_HFC_EN 0x00020000 /* h/w flow cntrl enabled */ |
| #define | SSCR_RX_RING_DCD 0x00040000 /* postRX record on delta-DCD */ |
| #define | SSCR_RX_RING_CTS 0x00080000 /* postRX record on delta-CTS */ |
| #define | SSCR_HIGH_SPD 0x00100000 /* 4X speed */ |
| #define | SSCR_DIAG 0x00200000 /* bypass clock divider */ |
| #define | SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */ |
| #define | SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */ |
| #define | SSCR_DMA_PAUSE 0x20000000 /* pause DMA */ |
| #define | SSCR_PAUSE_STATE 0x40000000 /* set when PAUSE takes effect*/ |
| #define | SSCR_RESET 0x80000000 /* reset DMA channels */ |
| #define | PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */ |
| #define | PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */ |
| #define | PROD_CONS_PTR_OFF 3 |
| #define | SRCIR_ARM 0x80000000 /* arm RX timer */ |
| #define | SHADOW_DR 0x00000001 /* data ready */ |
| #define | SHADOW_OE 0x00000002 /* overrun error */ |
| #define | SHADOW_PE 0x00000004 /* parity error */ |
| #define | SHADOW_FE 0x00000008 /* framing error */ |
| #define | SHADOW_BI 0x00000010 /* break interrupt */ |
| #define | SHADOW_THRE 0x00000020 /* transmit holding reg empty */ |
| #define | SHADOW_TEMT 0x00000040 /* transmit shift reg empty */ |
| #define | SHADOW_RFCE 0x00000080 /* char in RX fifo has error */ |
| #define | SHADOW_DCTS 0x00010000 /* delta clear to send */ |
| #define | SHADOW_DDCD 0x00080000 /* delta data carrier detect */ |
| #define | SHADOW_CTS 0x00100000 /* clear to send */ |
| #define | SHADOW_DCD 0x00800000 /* data carrier detect */ |
| #define | SHADOW_DTR 0x01000000 /* data terminal ready */ |
| #define | SHADOW_RTS 0x02000000 /* request to send */ |
| #define | SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */ |
| #define | SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */ |
| #define | SHADOW_LOOP 0x10000000 /* loopback enabled */ |
| #define | SRTR_CNT 0x00000fff /* reload value for RX timer */ |
| #define | SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */ |
| #define | SRTR_CNT_VAL_SHIFT 16 |
| #define | SRTR_HZ 16000 /* SRTR clock frequency */ |
| #define | SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */ |
| #define | SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */ |
| #define | SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */ |
| #define | SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */ |
| #define | SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */ |
| #define | SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */ |
| #define | SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */ |
| #define | SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */ |
| #define | SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */ |
| #define | SIO_IR_SB_TX_MT 0x00000200 |
| #define | SIO_IR_SB_RX_FULL 0x00000400 |
| #define | SIO_IR_SB_RX_HIGH 0x00000800 |
| #define | SIO_IR_SB_RX_TIMER 0x00001000 |
| #define | SIO_IR_SB_DELTA_DCD 0x00002000 |
| #define | SIO_IR_SB_DELTA_CTS 0x00004000 |
| #define | SIO_IR_SB_INT 0x00008000 |
| #define | SIO_IR_SB_TX_EXPLICIT 0x00010000 |
| #define | SIO_IR_SB_MEMERR 0x00020000 |
| #define | SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */ |
| #define | SIO_IR_PP_INTA 0x00080000 /* PP context A thru */ |
| #define | SIO_IR_PP_INTB 0x00100000 /* PP context B thru */ |
| #define | SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */ |
| #define | SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */ |
| #define | SIO_IR_RT_INT 0x08000000 /* RT output pulse */ |
| #define | SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */ |
| #define | SIO_IR_GEN_INT_SHIFT 28 |
| #define | SIO_IR_SA |
| #define | SIO_IR_SB |
| #define | SIO_IR_PP |
| #define | SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1) |
| #define | SIO_CR_CMD_PULSE_SHIFT 15 |
| #define | SIO_CR_SER_A_BASE_SHIFT 1 |
| #define | SIO_CR_SER_B_BASE_SHIFT 8 |
| #define | SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */ |
| #define | SIO_CR_ARB_DIAG_TXA 0x00000000 |
| #define | SIO_CR_ARB_DIAG_RXA 0x00080000 |
| #define | SIO_CR_ARB_DIAG_TXB 0x00100000 |
| #define | SIO_CR_ARB_DIAG_RXB 0x00180000 |
| #define | SIO_CR_ARB_DIAG_PP 0x00200000 |
| #define | SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */ |
| #define | GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */ |
| #define | GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */ |
| #define | GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */ |
| #define | GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */ |
| #define | GPPR_UARTB_MODESEL_PIN 6 /* GIO pin cntrling uartb modeselect */ |
| #define | GPPR_UARTA_MODESEL_PIN 7 /* GIO pin cntrling uarta modeselect */ |
| #define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */ |
| #define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */ |
| #define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */ |
| #define RXSB_DATA_VALID 0x80 /* FRAME_ERR PAR_ERR & BREAK valid */ |
| #define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */ |
| #define SBBR_L_SIZE 0x00000001 /* 0 1KB rings, 1 4KB rings */ |
| #define SHADOW_DDCD 0x00080000 /* delta data carrier detect */ |
| #define SHADOW_RFCE 0x00000080 /* char in RX fifo has error */ |
| #define SHADOW_TEMT 0x00000040 /* transmit shift reg empty */ |
| #define SHADOW_THRE 0x00000020 /* transmit holding reg empty */ |
| #define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */ |
| #define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */ |
| #define SIO_IR_PP |
| #define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1) |
| #define SIO_IR_SA |
| #define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */ |
| #define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */ |
| #define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */ |
| #define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */ |
| #define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */ |
| #define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */ |
| #define SIO_IR_SB |
| #define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */ |
| #define SSCR_PAUSE_STATE 0x40000000 /* set when PAUSE takes effect*/ |
| #define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */ |
| #define SSCR_RX_RING_CTS 0x00080000 /* postRX record on delta-CTS */ |
| #define SSCR_RX_RING_DCD 0x00040000 /* postRX record on delta-DCD */ |
| #define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */ |
| #define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */ |
| #define TXCB_MCR 0x80 /* data<7:0> to modem cntrl register */ |
1.8.2