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ioc3.h
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1 /*
2  * Copyright (C) 1999, 2000 Ralf Baechle
3  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
4  */
5 #ifndef _IOC3_H
6 #define _IOC3_H
7 
8 #include <linux/types.h>
9 
10 /* SUPERIO uart register map */
11 typedef volatile struct ioc3_uartregs {
12  union {
13  volatile u8 rbr; /* read only, DLAB == 0 */
14  volatile u8 thr; /* write only, DLAB == 0 */
15  volatile u8 dll; /* DLAB == 1 */
16  } u1;
17  union {
18  volatile u8 ier; /* DLAB == 0 */
19  volatile u8 dlm; /* DLAB == 1 */
20  } u2;
21  union {
22  volatile u8 iir; /* read only */
23  volatile u8 fcr; /* write only */
24  } u3;
25  volatile u8 iu_lcr;
26  volatile u8 iu_mcr;
27  volatile u8 iu_lsr;
28  volatile u8 iu_msr;
29  volatile u8 iu_scr;
30 } ioc3_uregs_t;
31 
32 #define iu_rbr u1.rbr
33 #define iu_thr u1.thr
34 #define iu_dll u1.dll
35 #define iu_ier u2.ier
36 #define iu_dlm u2.dlm
37 #define iu_iir u3.iir
38 #define iu_fcr u3.fcr
39 
40 struct ioc3_sioregs {
41  volatile u8 fill[0x141]; /* starts at 0x141 */
42 
43  volatile u8 uartc;
44  volatile u8 kbdcg;
45 
46  volatile u8 fill0[0x150 - 0x142 - 1];
47 
48  volatile u8 pp_data;
49  volatile u8 pp_dsr;
50  volatile u8 pp_dcr;
51 
52  volatile u8 fill1[0x158 - 0x152 - 1];
53 
54  volatile u8 pp_fifa;
55  volatile u8 pp_cfgb;
56  volatile u8 pp_ecr;
57 
58  volatile u8 fill2[0x168 - 0x15a - 1];
59 
60  volatile u8 rtcad;
61  volatile u8 rtcdat;
62 
63  volatile u8 fill3[0x170 - 0x169 - 1];
64 
65  struct ioc3_uartregs uartb; /* 0x20170 */
66  struct ioc3_uartregs uarta; /* 0x20178 */
67 };
68 
69 /* Register layout of IOC3 in configuration space. */
70 struct ioc3 {
71  volatile u32 pad0[7]; /* 0x00000 */
72  volatile u32 sio_ir; /* 0x0001c */
73  volatile u32 sio_ies; /* 0x00020 */
74  volatile u32 sio_iec; /* 0x00024 */
75  volatile u32 sio_cr; /* 0x00028 */
76  volatile u32 int_out; /* 0x0002c */
77  volatile u32 mcr; /* 0x00030 */
78 
79  /* General Purpose I/O registers */
80  volatile u32 gpcr_s; /* 0x00034 */
81  volatile u32 gpcr_c; /* 0x00038 */
82  volatile u32 gpdr; /* 0x0003c */
83  volatile u32 gppr_0; /* 0x00040 */
84  volatile u32 gppr_1; /* 0x00044 */
85  volatile u32 gppr_2; /* 0x00048 */
86  volatile u32 gppr_3; /* 0x0004c */
87  volatile u32 gppr_4; /* 0x00050 */
88  volatile u32 gppr_5; /* 0x00054 */
89  volatile u32 gppr_6; /* 0x00058 */
90  volatile u32 gppr_7; /* 0x0005c */
91  volatile u32 gppr_8; /* 0x00060 */
92  volatile u32 gppr_9; /* 0x00064 */
93  volatile u32 gppr_10; /* 0x00068 */
94  volatile u32 gppr_11; /* 0x0006c */
95  volatile u32 gppr_12; /* 0x00070 */
96  volatile u32 gppr_13; /* 0x00074 */
97  volatile u32 gppr_14; /* 0x00078 */
98  volatile u32 gppr_15; /* 0x0007c */
99 
100  /* Parallel Port Registers */
101  volatile u32 ppbr_h_a; /* 0x00080 */
102  volatile u32 ppbr_l_a; /* 0x00084 */
103  volatile u32 ppcr_a; /* 0x00088 */
104  volatile u32 ppcr; /* 0x0008c */
105  volatile u32 ppbr_h_b; /* 0x00090 */
106  volatile u32 ppbr_l_b; /* 0x00094 */
107  volatile u32 ppcr_b; /* 0x00098 */
108 
109  /* Keyboard and Mouse Registers */
110  volatile u32 km_csr; /* 0x0009c */
111  volatile u32 k_rd; /* 0x000a0 */
112  volatile u32 m_rd; /* 0x000a4 */
113  volatile u32 k_wd; /* 0x000a8 */
114  volatile u32 m_wd; /* 0x000ac */
115 
116  /* Serial Port Registers */
117  volatile u32 sbbr_h; /* 0x000b0 */
118  volatile u32 sbbr_l; /* 0x000b4 */
119  volatile u32 sscr_a; /* 0x000b8 */
120  volatile u32 stpir_a; /* 0x000bc */
121  volatile u32 stcir_a; /* 0x000c0 */
122  volatile u32 srpir_a; /* 0x000c4 */
123  volatile u32 srcir_a; /* 0x000c8 */
124  volatile u32 srtr_a; /* 0x000cc */
125  volatile u32 shadow_a; /* 0x000d0 */
126  volatile u32 sscr_b; /* 0x000d4 */
127  volatile u32 stpir_b; /* 0x000d8 */
128  volatile u32 stcir_b; /* 0x000dc */
129  volatile u32 srpir_b; /* 0x000e0 */
130  volatile u32 srcir_b; /* 0x000e4 */
131  volatile u32 srtr_b; /* 0x000e8 */
132  volatile u32 shadow_b; /* 0x000ec */
133 
134  /* Ethernet Registers */
135  volatile u32 emcr; /* 0x000f0 */
136  volatile u32 eisr; /* 0x000f4 */
137  volatile u32 eier; /* 0x000f8 */
138  volatile u32 ercsr; /* 0x000fc */
139  volatile u32 erbr_h; /* 0x00100 */
140  volatile u32 erbr_l; /* 0x00104 */
141  volatile u32 erbar; /* 0x00108 */
142  volatile u32 ercir; /* 0x0010c */
143  volatile u32 erpir; /* 0x00110 */
144  volatile u32 ertr; /* 0x00114 */
145  volatile u32 etcsr; /* 0x00118 */
146  volatile u32 ersr; /* 0x0011c */
147  volatile u32 etcdc; /* 0x00120 */
148  volatile u32 ebir; /* 0x00124 */
149  volatile u32 etbr_h; /* 0x00128 */
150  volatile u32 etbr_l; /* 0x0012c */
151  volatile u32 etcir; /* 0x00130 */
152  volatile u32 etpir; /* 0x00134 */
153  volatile u32 emar_h; /* 0x00138 */
154  volatile u32 emar_l; /* 0x0013c */
155  volatile u32 ehar_h; /* 0x00140 */
156  volatile u32 ehar_l; /* 0x00144 */
157  volatile u32 micr; /* 0x00148 */
158  volatile u32 midr_r; /* 0x0014c */
159  volatile u32 midr_w; /* 0x00150 */
160  volatile u32 pad1[(0x20000 - 0x00154) / 4];
161 
162  /* SuperIO Registers XXX */
163  struct ioc3_sioregs sregs; /* 0x20000 */
164  volatile u32 pad2[(0x40000 - 0x20180) / 4];
165 
166  /* SSRAM Diagnostic Access */
167  volatile u32 ssram[(0x80000 - 0x40000) / 4];
168 
169  /* Bytebus device offsets
170  0x80000 - Access to the generic devices selected with DEV0
171  0x9FFFF bytebus DEV_SEL_0
172  0xA0000 - Access to the generic devices selected with DEV1
173  0xBFFFF bytebus DEV_SEL_1
174  0xC0000 - Access to the generic devices selected with DEV2
175  0xDFFFF bytebus DEV_SEL_2
176  0xE0000 - Access to the generic devices selected with DEV3
177  0xFFFFF bytebus DEV_SEL_3 */
178 };
179 
180 /*
181  * Ethernet RX Buffer
182  */
183 struct ioc3_erxbuf {
184  u32 w0; /* first word (valid,bcnt,cksum) */
185  u32 err; /* second word various errors */
186  /* next comes n bytes of padding */
187  /* then the received ethernet frame itself */
188 };
189 
190 #define ERXBUF_IPCKSUM_MASK 0x0000ffff
191 #define ERXBUF_BYTECNT_MASK 0x07ff0000
192 #define ERXBUF_BYTECNT_SHIFT 16
193 #define ERXBUF_V 0x80000000
194 
195 #define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */
196 #define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */
197 #define ERXBUF_CODERR 0x00000004 /* aka RSV13 */
198 #define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */
199 #define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */
200 #define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */
201 #define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */
202 #define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */
203 #define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */
204 #define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */
205 #define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */
206 #define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */
207 
208 /*
209  * Ethernet TX Descriptor
210  */
211 #define ETXD_DATALEN 104
212 struct ioc3_etxd {
213  u32 cmd; /* command field */
214  u32 bufcnt; /* buffer counts field */
215  u64 p1; /* buffer pointer 1 */
216  u64 p2; /* buffer pointer 2 */
217  u8 data[ETXD_DATALEN]; /* opt. tx data */
218 };
219 
220 #define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */
221 #define ETXD_INTWHENDONE 0x00001000 /* intr when done */
222 #define ETXD_D0V 0x00010000 /* data 0 valid */
223 #define ETXD_B1V 0x00020000 /* buf 1 valid */
224 #define ETXD_B2V 0x00040000 /* buf 2 valid */
225 #define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */
226 #define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */
227 #define ETXD_CHKOFF_SHIFT 20
228 
229 #define ETXD_D0CNT_MASK 0x0000007f
230 #define ETXD_B1CNT_MASK 0x0007ff00
231 #define ETXD_B1CNT_SHIFT 8
232 #define ETXD_B2CNT_MASK 0x7ff00000
233 #define ETXD_B2CNT_SHIFT 20
234 
235 /*
236  * Bytebus device space
237  */
238 #define IOC3_BYTEBUS_DEV0 0x80000L
239 #define IOC3_BYTEBUS_DEV1 0xa0000L
240 #define IOC3_BYTEBUS_DEV2 0xc0000L
241 #define IOC3_BYTEBUS_DEV3 0xe0000L
242 
243 /* ------------------------------------------------------------------------- */
244 
245 /* Superio Registers (PIO Access) */
246 #define IOC3_SIO_BASE 0x20000
247 #define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141) /* UART Config */
248 #define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142) /* KBD Config */
249 #define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */
250 #define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168) /* Real Time Clock */
251 #define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE) /* UART B */
252 #define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE) /* UART A */
253 
254 /* SSRAM Diagnostic Access */
255 #define IOC3_SSRAM IOC3_RAM_OFF /* base of SSRAM diagnostic access */
256 #define IOC3_SSRAM_LEN 0x40000 /* 256kb (address space size, may not be fully populated) */
257 #define IOC3_SSRAM_DM 0x0000ffff /* data mask */
258 #define IOC3_SSRAM_PM 0x00010000 /* parity mask */
259 
260 /* bitmasks for PCI_SCR */
261 #define PCI_SCR_PAR_RESP_EN 0x00000040 /* enb PCI parity checking */
262 #define PCI_SCR_SERR_EN 0x00000100 /* enable the SERR# driver */
263 #define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */
264 #define PCI_SCR_RX_SERR (0x1 << 16)
265 #define PCI_SCR_DROP_MODE (0x1 << 17)
266 #define PCI_SCR_SIG_PAR_ERR (0x1 << 24)
267 #define PCI_SCR_SIG_TAR_ABRT (0x1 << 27)
268 #define PCI_SCR_RX_TAR_ABRT (0x1 << 28)
269 #define PCI_SCR_SIG_MST_ABRT (0x1 << 29)
270 #define PCI_SCR_SIG_SERR (0x1 << 30)
271 #define PCI_SCR_PAR_ERR (0x1 << 31)
272 
273 /* bitmasks for IOC3_KM_CSR */
274 #define KM_CSR_K_WRT_PEND 0x00000001 /* kbd port xmitting or resetting */
275 #define KM_CSR_M_WRT_PEND 0x00000002 /* mouse port xmitting or resetting */
276 #define KM_CSR_K_LCB 0x00000004 /* Line Cntrl Bit for last KBD write */
277 #define KM_CSR_M_LCB 0x00000008 /* same for mouse */
278 #define KM_CSR_K_DATA 0x00000010 /* state of kbd data line */
279 #define KM_CSR_K_CLK 0x00000020 /* state of kbd clock line */
280 #define KM_CSR_K_PULL_DATA 0x00000040 /* pull kbd data line low */
281 #define KM_CSR_K_PULL_CLK 0x00000080 /* pull kbd clock line low */
282 #define KM_CSR_M_DATA 0x00000100 /* state of ms data line */
283 #define KM_CSR_M_CLK 0x00000200 /* state of ms clock line */
284 #define KM_CSR_M_PULL_DATA 0x00000400 /* pull ms data line low */
285 #define KM_CSR_M_PULL_CLK 0x00000800 /* pull ms clock line low */
286 #define KM_CSR_EMM_MODE 0x00001000 /* emulation mode */
287 #define KM_CSR_SIM_MODE 0x00002000 /* clock X8 */
288 #define KM_CSR_K_SM_IDLE 0x00004000 /* Keyboard is idle */
289 #define KM_CSR_M_SM_IDLE 0x00008000 /* Mouse is idle */
290 #define KM_CSR_K_TO 0x00010000 /* Keyboard trying to send/receive */
291 #define KM_CSR_M_TO 0x00020000 /* Mouse trying to send/receive */
292 #define KM_CSR_K_TO_EN 0x00040000 /* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause
293  SIO_IR to assert */
294 #define KM_CSR_M_TO_EN 0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause
295  SIO_IR to assert */
296 #define KM_CSR_K_CLAMP_ONE 0x00100000 /* Pull K_CLK low after rec. one char */
297 #define KM_CSR_M_CLAMP_ONE 0x00200000 /* Pull M_CLK low after rec. one char */
298 #define KM_CSR_K_CLAMP_THREE 0x00400000 /* Pull K_CLK low after rec. three chars */
299 #define KM_CSR_M_CLAMP_THREE 0x00800000 /* Pull M_CLK low after rec. three char */
300 
301 /* bitmasks for IOC3_K_RD and IOC3_M_RD */
302 #define KM_RD_DATA_2 0x000000ff /* 3rd char recvd since last read */
303 #define KM_RD_DATA_2_SHIFT 0
304 #define KM_RD_DATA_1 0x0000ff00 /* 2nd char recvd since last read */
305 #define KM_RD_DATA_1_SHIFT 8
306 #define KM_RD_DATA_0 0x00ff0000 /* 1st char recvd since last read */
307 #define KM_RD_DATA_0_SHIFT 16
308 #define KM_RD_FRAME_ERR_2 0x01000000 /* framing or parity error in byte 2 */
309 #define KM_RD_FRAME_ERR_1 0x02000000 /* same for byte 1 */
310 #define KM_RD_FRAME_ERR_0 0x04000000 /* same for byte 0 */
311 
312 #define KM_RD_KBD_MSE 0x08000000 /* 0 if from kbd, 1 if from mouse */
313 #define KM_RD_OFLO 0x10000000 /* 4th char recvd before this read */
314 #define KM_RD_VALID_2 0x20000000 /* DATA_2 valid */
315 #define KM_RD_VALID_1 0x40000000 /* DATA_1 valid */
316 #define KM_RD_VALID_0 0x80000000 /* DATA_0 valid */
317 #define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2)
318 
319 /* bitmasks for IOC3_K_WD & IOC3_M_WD */
320 #define KM_WD_WRT_DATA 0x000000ff /* write to keyboard/mouse port */
321 #define KM_WD_WRT_DATA_SHIFT 0
322 
323 /* bitmasks for serial RX status byte */
324 #define RXSB_OVERRUN 0x01 /* char(s) lost */
325 #define RXSB_PAR_ERR 0x02 /* parity error */
326 #define RXSB_FRAME_ERR 0x04 /* framing error */
327 #define RXSB_BREAK 0x08 /* break character */
328 #define RXSB_CTS 0x10 /* state of CTS */
329 #define RXSB_DCD 0x20 /* state of DCD */
330 #define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */
331 #define RXSB_DATA_VALID 0x80 /* data byte, FRAME_ERR PAR_ERR & BREAK valid */
332 
333 /* bitmasks for serial TX control byte */
334 #define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */
335 #define TXCB_INVALID 0x00 /* byte is invalid */
336 #define TXCB_VALID 0x40 /* byte is valid */
337 #define TXCB_MCR 0x80 /* data<7:0> to modem control register */
338 #define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */
339 
340 /* bitmasks for IOC3_SBBR_L */
341 #define SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */
342 #define SBBR_L_BASE 0xfffff000 /* lower serial ring base addr */
343 
344 /* bitmasks for IOC3_SSCR_<A:B> */
345 #define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */
346 #define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
347 #define SSCR_HFC_EN 0x00020000 /* hardware flow control enabled */
348 #define SSCR_RX_RING_DCD 0x00040000 /* post RX record on delta-DCD */
349 #define SSCR_RX_RING_CTS 0x00080000 /* post RX record on delta-CTS */
350 #define SSCR_HIGH_SPD 0x00100000 /* 4X speed */
351 #define SSCR_DIAG 0x00200000 /* bypass clock divider for sim */
352 #define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */
353 #define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */
354 #define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */
355 #define SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */
356 #define SSCR_RESET 0x80000000 /* reset DMA channels */
357 
358 /* all producer/comsumer pointers are the same bitfield */
359 #define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */
360 #define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */
361 #define PROD_CONS_PTR_OFF 3
362 
363 /* bitmasks for IOC3_SRCIR_<A:B> */
364 #define SRCIR_ARM 0x80000000 /* arm RX timer */
365 
366 /* bitmasks for IOC3_SRPIR_<A:B> */
367 #define SRPIR_BYTE_CNT 0x07000000 /* bytes in packer */
368 #define SRPIR_BYTE_CNT_SHIFT 24
369 
370 /* bitmasks for IOC3_STCIR_<A:B> */
371 #define STCIR_BYTE_CNT 0x0f000000 /* bytes in unpacker */
372 #define STCIR_BYTE_CNT_SHIFT 24
373 
374 /* bitmasks for IOC3_SHADOW_<A:B> */
375 #define SHADOW_DR 0x00000001 /* data ready */
376 #define SHADOW_OE 0x00000002 /* overrun error */
377 #define SHADOW_PE 0x00000004 /* parity error */
378 #define SHADOW_FE 0x00000008 /* framing error */
379 #define SHADOW_BI 0x00000010 /* break interrupt */
380 #define SHADOW_THRE 0x00000020 /* transmit holding register empty */
381 #define SHADOW_TEMT 0x00000040 /* transmit shift register empty */
382 #define SHADOW_RFCE 0x00000080 /* char in RX fifo has an error */
383 #define SHADOW_DCTS 0x00010000 /* delta clear to send */
384 #define SHADOW_DDCD 0x00080000 /* delta data carrier detect */
385 #define SHADOW_CTS 0x00100000 /* clear to send */
386 #define SHADOW_DCD 0x00800000 /* data carrier detect */
387 #define SHADOW_DTR 0x01000000 /* data terminal ready */
388 #define SHADOW_RTS 0x02000000 /* request to send */
389 #define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
390 #define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
391 #define SHADOW_LOOP 0x10000000 /* loopback enabled */
392 
393 /* bitmasks for IOC3_SRTR_<A:B> */
394 #define SRTR_CNT 0x00000fff /* reload value for RX timer */
395 #define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */
396 #define SRTR_CNT_VAL_SHIFT 16
397 #define SRTR_HZ 16000 /* SRTR clock frequency */
398 
399 /* bitmasks for IOC3_SIO_IR, IOC3_SIO_IEC and IOC3_SIO_IES */
400 #define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */
401 #define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */
402 #define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */
403 #define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */
404 #define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */
405 #define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */
406 #define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */
407 #define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */
408 #define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */
409 #define SIO_IR_SB_TX_MT 0x00000200 /* */
410 #define SIO_IR_SB_RX_FULL 0x00000400 /* */
411 #define SIO_IR_SB_RX_HIGH 0x00000800 /* */
412 #define SIO_IR_SB_RX_TIMER 0x00001000 /* */
413 #define SIO_IR_SB_DELTA_DCD 0x00002000 /* */
414 #define SIO_IR_SB_DELTA_CTS 0x00004000 /* */
415 #define SIO_IR_SB_INT 0x00008000 /* */
416 #define SIO_IR_SB_TX_EXPLICIT 0x00010000 /* */
417 #define SIO_IR_SB_MEMERR 0x00020000 /* */
418 #define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */
419 #define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */
420 #define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */
421 #define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */
422 #define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */
423 #define SIO_IR_RT_INT 0x08000000 /* RT output pulse */
424 #define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */
425 #define SIO_IR_GEN_INT_SHIFT 28
426 
427 /* per device interrupt masks */
428 #define SIO_IR_SA (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \
429  SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \
430  SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \
431  SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \
432  SIO_IR_SA_MEMERR)
433 #define SIO_IR_SB (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \
434  SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \
435  SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \
436  SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \
437  SIO_IR_SB_MEMERR)
438 #define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | \
439  SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
440 #define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
441 
442 /* macro to load pending interrupts */
443 #define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \
444  PCI_INW(&((mem)->sio_ies_ro)))
445 
446 /* bitmasks for SIO_CR */
447 #define SIO_CR_SIO_RESET 0x00000001 /* reset the SIO */
448 #define SIO_CR_SER_A_BASE 0x000000fe /* DMA poll addr port A */
449 #define SIO_CR_SER_A_BASE_SHIFT 1
450 #define SIO_CR_SER_B_BASE 0x00007f00 /* DMA poll addr port B */
451 #define SIO_CR_SER_B_BASE_SHIFT 8
452 #define SIO_SR_CMD_PULSE 0x00078000 /* byte bus strobe length */
453 #define SIO_CR_CMD_PULSE_SHIFT 15
454 #define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */
455 #define SIO_CR_ARB_DIAG_TXA 0x00000000
456 #define SIO_CR_ARB_DIAG_RXA 0x00080000
457 #define SIO_CR_ARB_DIAG_TXB 0x00100000
458 #define SIO_CR_ARB_DIAG_RXB 0x00180000
459 #define SIO_CR_ARB_DIAG_PP 0x00200000
460 #define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */
461 
462 /* bitmasks for INT_OUT */
463 #define INT_OUT_COUNT 0x0000ffff /* pulse interval timer */
464 #define INT_OUT_MODE 0x00070000 /* mode mask */
465 #define INT_OUT_MODE_0 0x00000000 /* set output to 0 */
466 #define INT_OUT_MODE_1 0x00040000 /* set output to 1 */
467 #define INT_OUT_MODE_1PULSE 0x00050000 /* send 1 pulse */
468 #define INT_OUT_MODE_PULSES 0x00060000 /* send 1 pulse every interval */
469 #define INT_OUT_MODE_SQW 0x00070000 /* toggle output every interval */
470 #define INT_OUT_DIAG 0x40000000 /* diag mode */
471 #define INT_OUT_INT_OUT 0x80000000 /* current state of INT_OUT */
472 
473 /* time constants for INT_OUT */
474 #define INT_OUT_NS_PER_TICK (30 * 260) /* 30 ns PCI clock, divisor=260 */
475 #define INT_OUT_TICKS_PER_PULSE 3 /* outgoing pulse lasts 3 ticks */
476 #define INT_OUT_US_TO_COUNT(x) /* convert uS to a count value */ \
477  (((x) * 10 + INT_OUT_NS_PER_TICK / 200) * \
478  100 / INT_OUT_NS_PER_TICK - 1)
479 #define INT_OUT_COUNT_TO_US(x) /* convert count value to uS */ \
480  (((x) + 1) * INT_OUT_NS_PER_TICK / 1000)
481 #define INT_OUT_MIN_TICKS 3 /* min period is width of pulse in "ticks" */
482 #define INT_OUT_MAX_TICKS INT_OUT_COUNT /* largest possible count */
483 
484 /* bitmasks for GPCR */
485 #define GPCR_DIR 0x000000ff /* tristate pin input or output */
486 #define GPCR_DIR_PIN(x) (1<<(x)) /* access one of the DIR bits */
487 #define GPCR_EDGE 0x000f0000 /* extint edge or level sensitive */
488 #define GPCR_EDGE_PIN(x) (1<<((x)+15)) /* access one of the EDGE bits */
489 
490 /* values for GPCR */
491 #define GPCR_INT_OUT_EN 0x00100000 /* enable INT_OUT to pin 0 */
492 #define GPCR_MLAN_EN 0x00200000 /* enable MCR to pin 8 */
493 #define GPCR_DIR_SERA_XCVR 0x00000080 /* Port A Transceiver select enable */
494 #define GPCR_DIR_SERB_XCVR 0x00000040 /* Port B Transceiver select enable */
495 #define GPCR_DIR_PHY_RST 0x00000020 /* ethernet PHY reset enable */
496 
497 /* defs for some of the generic I/O pins */
498 #define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */
499 #define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */
500 #define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */
501 
502 #define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */
503 #define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin controlling uart b mode select */
504 #define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin controlling uart a mode select */
505 
506 #define EMCR_DUPLEX 0x00000001
507 #define EMCR_PROMISC 0x00000002
508 #define EMCR_PADEN 0x00000004
509 #define EMCR_RXOFF_MASK 0x000001f8
510 #define EMCR_RXOFF_SHIFT 3
511 #define EMCR_RAMPAR 0x00000200
512 #define EMCR_BADPAR 0x00000800
513 #define EMCR_BUFSIZ 0x00001000
514 #define EMCR_TXDMAEN 0x00002000
515 #define EMCR_TXEN 0x00004000
516 #define EMCR_RXDMAEN 0x00008000
517 #define EMCR_RXEN 0x00010000
518 #define EMCR_LOOPBACK 0x00020000
519 #define EMCR_ARB_DIAG 0x001c0000
520 #define EMCR_ARB_DIAG_IDLE 0x00200000
521 #define EMCR_RST 0x80000000
522 
523 #define EISR_RXTIMERINT 0x00000001
524 #define EISR_RXTHRESHINT 0x00000002
525 #define EISR_RXOFLO 0x00000004
526 #define EISR_RXBUFOFLO 0x00000008
527 #define EISR_RXMEMERR 0x00000010
528 #define EISR_RXPARERR 0x00000020
529 #define EISR_TXEMPTY 0x00010000
530 #define EISR_TXRTRY 0x00020000
531 #define EISR_TXEXDEF 0x00040000
532 #define EISR_TXLCOL 0x00080000
533 #define EISR_TXGIANT 0x00100000
534 #define EISR_TXBUFUFLO 0x00200000
535 #define EISR_TXEXPLICIT 0x00400000
536 #define EISR_TXCOLLWRAP 0x00800000
537 #define EISR_TXDEFERWRAP 0x01000000
538 #define EISR_TXMEMERR 0x02000000
539 #define EISR_TXPARERR 0x04000000
540 
541 #define ERCSR_THRESH_MASK 0x000001ff /* enet RX threshold */
542 #define ERCSR_RX_TMR 0x40000000 /* simulation only */
543 #define ERCSR_DIAG_OFLO 0x80000000 /* simulation only */
544 
545 #define ERBR_ALIGNMENT 4096
546 #define ERBR_L_RXRINGBASE_MASK 0xfffff000
547 
548 #define ERBAR_BARRIER_BIT 0x0100
549 #define ERBAR_RXBARR_MASK 0xffff0000
550 #define ERBAR_RXBARR_SHIFT 16
551 
552 #define ERCIR_RXCONSUME_MASK 0x00000fff
553 
554 #define ERPIR_RXPRODUCE_MASK 0x00000fff
555 #define ERPIR_ARM 0x80000000
556 
557 #define ERTR_CNT_MASK 0x000007ff
558 
559 #define ETCSR_IPGT_MASK 0x0000007f
560 #define ETCSR_IPGR1_MASK 0x00007f00
561 #define ETCSR_IPGR1_SHIFT 8
562 #define ETCSR_IPGR2_MASK 0x007f0000
563 #define ETCSR_IPGR2_SHIFT 16
564 #define ETCSR_NOTXCLK 0x80000000
565 
566 #define ETCDC_COLLCNT_MASK 0x0000ffff
567 #define ETCDC_DEFERCNT_MASK 0xffff0000
568 #define ETCDC_DEFERCNT_SHIFT 16
569 
570 #define ETBR_ALIGNMENT (64*1024)
571 #define ETBR_L_RINGSZ_MASK 0x00000001
572 #define ETBR_L_RINGSZ128 0
573 #define ETBR_L_RINGSZ512 1
574 #define ETBR_L_TXRINGBASE_MASK 0xffffc000
575 
576 #define ETCIR_TXCONSUME_MASK 0x0000ffff
577 #define ETCIR_IDLE 0x80000000
578 
579 #define ETPIR_TXPRODUCE_MASK 0x0000ffff
580 
581 #define EBIR_TXBUFPROD_MASK 0x0000001f
582 #define EBIR_TXBUFCONS_MASK 0x00001f00
583 #define EBIR_TXBUFCONS_SHIFT 8
584 #define EBIR_RXBUFPROD_MASK 0x007fc000
585 #define EBIR_RXBUFPROD_SHIFT 14
586 #define EBIR_RXBUFCONS_MASK 0xff800000
587 #define EBIR_RXBUFCONS_SHIFT 23
588 
589 #define MICR_REGADDR_MASK 0x0000001f
590 #define MICR_PHYADDR_MASK 0x000003e0
591 #define MICR_PHYADDR_SHIFT 5
592 #define MICR_READTRIG 0x00000400
593 #define MICR_BUSY 0x00000800
594 
595 #define MIDR_DATA_MASK 0x0000ffff
596 
597 #define ERXBUF_IPCKSUM_MASK 0x0000ffff
598 #define ERXBUF_BYTECNT_MASK 0x07ff0000
599 #define ERXBUF_BYTECNT_SHIFT 16
600 #define ERXBUF_V 0x80000000
601 
602 #define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */
603 #define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */
604 #define ERXBUF_CODERR 0x00000004 /* aka RSV13 */
605 #define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */
606 #define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */
607 #define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */
608 #define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */
609 #define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */
610 #define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */
611 #define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */
612 #define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */
613 #define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */
614 
615 #define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */
616 #define ETXD_INTWHENDONE 0x00001000 /* intr when done */
617 #define ETXD_D0V 0x00010000 /* data 0 valid */
618 #define ETXD_B1V 0x00020000 /* buf 1 valid */
619 #define ETXD_B2V 0x00040000 /* buf 2 valid */
620 #define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */
621 #define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */
622 #define ETXD_CHKOFF_SHIFT 20
623 
624 #define ETXD_D0CNT_MASK 0x0000007f
625 #define ETXD_B1CNT_MASK 0x0007ff00
626 #define ETXD_B1CNT_SHIFT 8
627 #define ETXD_B2CNT_MASK 0x7ff00000
628 #define ETXD_B2CNT_SHIFT 20
629 
630 typedef enum ioc3_subdevs_e {
631  ioc3_subdev_ether,
632  ioc3_subdev_generic,
633  ioc3_subdev_nic,
634  ioc3_subdev_kbms,
635  ioc3_subdev_ttya,
636  ioc3_subdev_ttyb,
637  ioc3_subdev_ecpp,
638  ioc3_subdev_rt,
639  ioc3_nsubdevs
640 } ioc3_subdev_t;
641 
642 /* subdevice disable bits,
643  * from the standard INFO_LBL_SUBDEVS
644  */
645 #define IOC3_SDB_ETHER (1<<ioc3_subdev_ether)
646 #define IOC3_SDB_GENERIC (1<<ioc3_subdev_generic)
647 #define IOC3_SDB_NIC (1<<ioc3_subdev_nic)
648 #define IOC3_SDB_KBMS (1<<ioc3_subdev_kbms)
649 #define IOC3_SDB_TTYA (1<<ioc3_subdev_ttya)
650 #define IOC3_SDB_TTYB (1<<ioc3_subdev_ttyb)
651 #define IOC3_SDB_ECPP (1<<ioc3_subdev_ecpp)
652 #define IOC3_SDB_RT (1<<ioc3_subdev_rt)
653 
654 #define IOC3_ALL_SUBDEVS ((1<<ioc3_nsubdevs)-1)
655 
656 #define IOC3_SDB_SERIAL (IOC3_SDB_TTYA|IOC3_SDB_TTYB)
657 
658 #define IOC3_STD_SUBDEVS IOC3_ALL_SUBDEVS
659 
660 #define IOC3_INTA_SUBDEVS IOC3_SDB_ETHER
661 #define IOC3_INTB_SUBDEVS (IOC3_SDB_GENERIC|IOC3_SDB_KBMS|IOC3_SDB_SERIAL|IOC3_SDB_ECPP|IOC3_SDB_RT)
662 
663 #endif /* _IOC3_H */
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