#include <linux/types.h>

Data Structures
struct	ioc3_uartregs

struct	ioc3_sioregs

struct	ioc3

struct	ioc3_erxbuf

struct	ioc3_etxd

Macros
#define	iu_rbr u1.rbr

#define	iu_thr u1.thr

#define	iu_dll u1.dll

#define	iu_ier u2.ier

#define	iu_dlm u2.dlm

#define	iu_iir u3.iir

#define	iu_fcr u3.fcr

#define	ERXBUF_IPCKSUM_MASK 0x0000ffff

#define	ERXBUF_BYTECNT_MASK 0x07ff0000

#define	ERXBUF_BYTECNT_SHIFT 16

#define	ERXBUF_V 0x80000000

#define	ERXBUF_CRCERR 0x00000001 /* aka RSV15 */

#define	ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */

#define	ERXBUF_CODERR 0x00000004 /* aka RSV13 */

#define	ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */

#define	ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */

#define	ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */

#define	ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */

#define	ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */

#define	ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */

#define	ERXBUF_BADPKT 0x20000000 /* aka RSV20 */

#define	ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */

#define	ERXBUF_CARRIER 0x80000000 /* aka RSV22 */

#define	ETXD_DATALEN 104

#define	ETXD_BYTECNT_MASK 0x000007ff /* total byte count */

#define	ETXD_INTWHENDONE 0x00001000 /* intr when done */

#define	ETXD_D0V 0x00010000 /* data 0 valid */

#define	ETXD_B1V 0x00020000 /* buf 1 valid */

#define	ETXD_B2V 0x00040000 /* buf 2 valid */

#define	ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */

#define	ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */

#define	ETXD_CHKOFF_SHIFT 20

#define	ETXD_D0CNT_MASK 0x0000007f

#define	ETXD_B1CNT_MASK 0x0007ff00

#define	ETXD_B1CNT_SHIFT 8

#define	ETXD_B2CNT_MASK 0x7ff00000

#define	ETXD_B2CNT_SHIFT 20

#define	IOC3_BYTEBUS_DEV0 0x80000L

#define	IOC3_BYTEBUS_DEV1 0xa0000L

#define	IOC3_BYTEBUS_DEV2 0xc0000L

#define	IOC3_BYTEBUS_DEV3 0xe0000L

#define	IOC3_SIO_BASE 0x20000

#define	IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141) /* UART Config */

#define	IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142) /* KBD Config */

#define	IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */

#define	IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168) /* Real Time Clock */

#define	IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE) /* UART B */

#define	IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE) /* UART A */

#define	IOC3_SSRAM IOC3_RAM_OFF /* base of SSRAM diagnostic access */

#define	IOC3_SSRAM_LEN 0x40000 /* 256kb (address space size, may not be fully populated) */

#define	IOC3_SSRAM_DM 0x0000ffff /* data mask */

#define	IOC3_SSRAM_PM 0x00010000 /* parity mask */

#define	PCI_SCR_PAR_RESP_EN 0x00000040 /* enb PCI parity checking */

#define	PCI_SCR_SERR_EN 0x00000100 /* enable the SERR# driver */

#define	PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */

#define	PCI_SCR_RX_SERR (0x1 << 16)

#define	PCI_SCR_DROP_MODE (0x1 << 17)

#define	PCI_SCR_SIG_PAR_ERR (0x1 << 24)

#define	PCI_SCR_SIG_TAR_ABRT (0x1 << 27)

#define	PCI_SCR_RX_TAR_ABRT (0x1 << 28)

#define	PCI_SCR_SIG_MST_ABRT (0x1 << 29)

#define	PCI_SCR_SIG_SERR (0x1 << 30)

#define	PCI_SCR_PAR_ERR (0x1 << 31)

#define	KM_CSR_K_WRT_PEND 0x00000001 /* kbd port xmitting or resetting */

#define	KM_CSR_M_WRT_PEND 0x00000002 /* mouse port xmitting or resetting */

#define	KM_CSR_K_LCB 0x00000004 /* Line Cntrl Bit for last KBD write */

#define	KM_CSR_M_LCB 0x00000008 /* same for mouse */

#define	KM_CSR_K_DATA 0x00000010 /* state of kbd data line */

#define	KM_CSR_K_CLK 0x00000020 /* state of kbd clock line */

#define	KM_CSR_K_PULL_DATA 0x00000040 /* pull kbd data line low */

#define	KM_CSR_K_PULL_CLK 0x00000080 /* pull kbd clock line low */

#define	KM_CSR_M_DATA 0x00000100 /* state of ms data line */

#define	KM_CSR_M_CLK 0x00000200 /* state of ms clock line */

#define	KM_CSR_M_PULL_DATA 0x00000400 /* pull ms data line low */

#define	KM_CSR_M_PULL_CLK 0x00000800 /* pull ms clock line low */

#define	KM_CSR_EMM_MODE 0x00001000 /* emulation mode */

#define	KM_CSR_SIM_MODE 0x00002000 /* clock X8 */

#define	KM_CSR_K_SM_IDLE 0x00004000 /* Keyboard is idle */

#define	KM_CSR_M_SM_IDLE 0x00008000 /* Mouse is idle */

#define	KM_CSR_K_TO 0x00010000 /* Keyboard trying to send/receive */

#define	KM_CSR_M_TO 0x00020000 /* Mouse trying to send/receive */

#define	KM_CSR_K_TO_EN

#define	KM_CSR_M_TO_EN

#define	KM_CSR_K_CLAMP_ONE 0x00100000 /* Pull K_CLK low after rec. one char */

#define	KM_CSR_M_CLAMP_ONE 0x00200000 /* Pull M_CLK low after rec. one char */

#define	KM_CSR_K_CLAMP_THREE 0x00400000 /* Pull K_CLK low after rec. three chars */

#define	KM_CSR_M_CLAMP_THREE 0x00800000 /* Pull M_CLK low after rec. three char */

#define	KM_RD_DATA_2 0x000000ff /* 3rd char recvd since last read */

#define	KM_RD_DATA_2_SHIFT 0

#define	KM_RD_DATA_1 0x0000ff00 /* 2nd char recvd since last read */

#define	KM_RD_DATA_1_SHIFT 8

#define	KM_RD_DATA_0 0x00ff0000 /* 1st char recvd since last read */

#define	KM_RD_DATA_0_SHIFT 16

#define	KM_RD_FRAME_ERR_2 0x01000000 /* framing or parity error in byte 2 */

#define	KM_RD_FRAME_ERR_1 0x02000000 /* same for byte 1 */

#define	KM_RD_FRAME_ERR_0 0x04000000 /* same for byte 0 */

#define	KM_RD_KBD_MSE 0x08000000 /* 0 if from kbd, 1 if from mouse */

#define	KM_RD_OFLO 0x10000000 /* 4th char recvd before this read */

#define	KM_RD_VALID_2 0x20000000 /* DATA_2 valid */

#define	KM_RD_VALID_1 0x40000000 /* DATA_1 valid */

#define	KM_RD_VALID_0 0x80000000 /* DATA_0 valid */

#define	KM_RD_VALID_ALL (KM_RD_VALID_0\|KM_RD_VALID_1\|KM_RD_VALID_2)

#define	KM_WD_WRT_DATA 0x000000ff /* write to keyboard/mouse port */

#define	KM_WD_WRT_DATA_SHIFT 0

#define	RXSB_OVERRUN 0x01 /* char(s) lost */

#define	RXSB_PAR_ERR 0x02 /* parity error */

#define	RXSB_FRAME_ERR 0x04 /* framing error */

#define	RXSB_BREAK 0x08 /* break character */

#define	RXSB_CTS 0x10 /* state of CTS */

#define	RXSB_DCD 0x20 /* state of DCD */

#define	RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */

#define	RXSB_DATA_VALID 0x80 /* data byte, FRAME_ERR PAR_ERR & BREAK valid */

#define	TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */

#define	TXCB_INVALID 0x00 /* byte is invalid */

#define	TXCB_VALID 0x40 /* byte is valid */

#define	TXCB_MCR 0x80 /* data<7:0> to modem control register */

#define	TXCB_DELAY 0xc0 /* delay data<7:0> mSec */

#define	SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */

#define	SBBR_L_BASE 0xfffff000 /* lower serial ring base addr */

#define	SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */

#define	SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */

#define	SSCR_HFC_EN 0x00020000 /* hardware flow control enabled */

#define	SSCR_RX_RING_DCD 0x00040000 /* post RX record on delta-DCD */

#define	SSCR_RX_RING_CTS 0x00080000 /* post RX record on delta-CTS */

#define	SSCR_HIGH_SPD 0x00100000 /* 4X speed */

#define	SSCR_DIAG 0x00200000 /* bypass clock divider for sim */

#define	SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */

#define	SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */

#define	SSCR_DMA_PAUSE 0x20000000 /* pause DMA */

#define	SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */

#define	SSCR_RESET 0x80000000 /* reset DMA channels */

#define	PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */

#define	PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */

#define	PROD_CONS_PTR_OFF 3

#define	SRCIR_ARM 0x80000000 /* arm RX timer */

#define	SRPIR_BYTE_CNT 0x07000000 /* bytes in packer */

#define	SRPIR_BYTE_CNT_SHIFT 24

#define	STCIR_BYTE_CNT 0x0f000000 /* bytes in unpacker */

#define	STCIR_BYTE_CNT_SHIFT 24

#define	SHADOW_DR 0x00000001 /* data ready */

#define	SHADOW_OE 0x00000002 /* overrun error */

#define	SHADOW_PE 0x00000004 /* parity error */

#define	SHADOW_FE 0x00000008 /* framing error */

#define	SHADOW_BI 0x00000010 /* break interrupt */

#define	SHADOW_THRE 0x00000020 /* transmit holding register empty */

#define	SHADOW_TEMT 0x00000040 /* transmit shift register empty */

#define	SHADOW_RFCE 0x00000080 /* char in RX fifo has an error */

#define	SHADOW_DCTS 0x00010000 /* delta clear to send */

#define	SHADOW_DDCD 0x00080000 /* delta data carrier detect */

#define	SHADOW_CTS 0x00100000 /* clear to send */

#define	SHADOW_DCD 0x00800000 /* data carrier detect */

#define	SHADOW_DTR 0x01000000 /* data terminal ready */

#define	SHADOW_RTS 0x02000000 /* request to send */

#define	SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */

#define	SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */

#define	SHADOW_LOOP 0x10000000 /* loopback enabled */

#define	SRTR_CNT 0x00000fff /* reload value for RX timer */

#define	SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */

#define	SRTR_CNT_VAL_SHIFT 16

#define	SRTR_HZ 16000 /* SRTR clock frequency */

#define	SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */

#define	SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */

#define	SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */

#define	SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */

#define	SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */

#define	SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */

#define	SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */

#define	SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */

#define	SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */

#define	SIO_IR_SB_TX_MT 0x00000200 /* */

#define	SIO_IR_SB_RX_FULL 0x00000400 /* */

#define	SIO_IR_SB_RX_HIGH 0x00000800 /* */

#define	SIO_IR_SB_RX_TIMER 0x00001000 /* */

#define	SIO_IR_SB_DELTA_DCD 0x00002000 /* */

#define	SIO_IR_SB_DELTA_CTS 0x00004000 /* */

#define	SIO_IR_SB_INT 0x00008000 /* */

#define	SIO_IR_SB_TX_EXPLICIT 0x00010000 /* */

#define	SIO_IR_SB_MEMERR 0x00020000 /* */

#define	SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */

#define	SIO_IR_PP_INTA 0x00080000 /* PP context A thru */

#define	SIO_IR_PP_INTB 0x00100000 /* PP context B thru */

#define	SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */

#define	SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */

#define	SIO_IR_RT_INT 0x08000000 /* RT output pulse */

#define	SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */

#define	SIO_IR_GEN_INT_SHIFT 28

#define	SIO_IR_SA

#define	SIO_IR_SB

#define	SIO_IR_PP

#define	SIO_IR_RT (SIO_IR_RT_INT \| SIO_IR_GEN_INT1)

#define	IOC3_PENDING_INTRS(mem)

#define	SIO_CR_SIO_RESET 0x00000001 /* reset the SIO */

#define	SIO_CR_SER_A_BASE 0x000000fe /* DMA poll addr port A */

#define	SIO_CR_SER_A_BASE_SHIFT 1

#define	SIO_CR_SER_B_BASE 0x00007f00 /* DMA poll addr port B */

#define	SIO_CR_SER_B_BASE_SHIFT 8

#define	SIO_SR_CMD_PULSE 0x00078000 /* byte bus strobe length */

#define	SIO_CR_CMD_PULSE_SHIFT 15

#define	SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */

#define	SIO_CR_ARB_DIAG_TXA 0x00000000

#define	SIO_CR_ARB_DIAG_RXA 0x00080000

#define	SIO_CR_ARB_DIAG_TXB 0x00100000

#define	SIO_CR_ARB_DIAG_RXB 0x00180000

#define	SIO_CR_ARB_DIAG_PP 0x00200000

#define	SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */

#define	INT_OUT_COUNT 0x0000ffff /* pulse interval timer */

#define	INT_OUT_MODE 0x00070000 /* mode mask */

#define	INT_OUT_MODE_0 0x00000000 /* set output to 0 */

#define	INT_OUT_MODE_1 0x00040000 /* set output to 1 */

#define	INT_OUT_MODE_1PULSE 0x00050000 /* send 1 pulse */

#define	INT_OUT_MODE_PULSES 0x00060000 /* send 1 pulse every interval */

#define	INT_OUT_MODE_SQW 0x00070000 /* toggle output every interval */

#define	INT_OUT_DIAG 0x40000000 /* diag mode */

#define	INT_OUT_INT_OUT 0x80000000 /* current state of INT_OUT */

#define	INT_OUT_NS_PER_TICK (30 * 260) /* 30 ns PCI clock, divisor=260 */

#define	INT_OUT_TICKS_PER_PULSE 3 /* outgoing pulse lasts 3 ticks */

#define	INT_OUT_US_TO_COUNT(x)

#define	INT_OUT_COUNT_TO_US(x)

#define	INT_OUT_MIN_TICKS 3 /* min period is width of pulse in "ticks" */

#define	INT_OUT_MAX_TICKS INT_OUT_COUNT /* largest possible count */

#define	GPCR_DIR 0x000000ff /* tristate pin input or output */

#define	GPCR_DIR_PIN(x) (1<<(x)) /* access one of the DIR bits */

#define	GPCR_EDGE 0x000f0000 /* extint edge or level sensitive */

#define	GPCR_EDGE_PIN(x) (1<<((x)+15)) /* access one of the EDGE bits */

#define	GPCR_INT_OUT_EN 0x00100000 /* enable INT_OUT to pin 0 */

#define	GPCR_MLAN_EN 0x00200000 /* enable MCR to pin 8 */

#define	GPCR_DIR_SERA_XCVR 0x00000080 /* Port A Transceiver select enable */

#define	GPCR_DIR_SERB_XCVR 0x00000040 /* Port B Transceiver select enable */

#define	GPCR_DIR_PHY_RST 0x00000020 /* ethernet PHY reset enable */

#define	GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */

#define	GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */

#define	GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */

#define	GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */

#define	GPPR_UARTB_MODESEL_PIN 6 /* GIO pin controlling uart b mode select */

#define	GPPR_UARTA_MODESEL_PIN 7 /* GIO pin controlling uart a mode select */

#define	EMCR_DUPLEX 0x00000001

#define	EMCR_PROMISC 0x00000002

#define	EMCR_PADEN 0x00000004

#define	EMCR_RXOFF_MASK 0x000001f8

#define	EMCR_RXOFF_SHIFT 3

#define	EMCR_RAMPAR 0x00000200

#define	EMCR_BADPAR 0x00000800

#define	EMCR_BUFSIZ 0x00001000

#define	EMCR_TXDMAEN 0x00002000

#define	EMCR_TXEN 0x00004000

#define	EMCR_RXDMAEN 0x00008000

#define	EMCR_RXEN 0x00010000

#define	EMCR_LOOPBACK 0x00020000

#define	EMCR_ARB_DIAG 0x001c0000

#define	EMCR_ARB_DIAG_IDLE 0x00200000

#define	EMCR_RST 0x80000000

#define	EISR_RXTIMERINT 0x00000001

#define	EISR_RXTHRESHINT 0x00000002

#define	EISR_RXOFLO 0x00000004

#define	EISR_RXBUFOFLO 0x00000008

#define	EISR_RXMEMERR 0x00000010

#define	EISR_RXPARERR 0x00000020

#define	EISR_TXEMPTY 0x00010000

#define	EISR_TXRTRY 0x00020000

#define	EISR_TXEXDEF 0x00040000

#define	EISR_TXLCOL 0x00080000

#define	EISR_TXGIANT 0x00100000

#define	EISR_TXBUFUFLO 0x00200000

#define	EISR_TXEXPLICIT 0x00400000

#define	EISR_TXCOLLWRAP 0x00800000

#define	EISR_TXDEFERWRAP 0x01000000

#define	EISR_TXMEMERR 0x02000000

#define	EISR_TXPARERR 0x04000000

#define	ERCSR_THRESH_MASK 0x000001ff /* enet RX threshold */

#define	ERCSR_RX_TMR 0x40000000 /* simulation only */

#define	ERCSR_DIAG_OFLO 0x80000000 /* simulation only */

#define	ERBR_ALIGNMENT 4096

#define	ERBR_L_RXRINGBASE_MASK 0xfffff000

#define	ERBAR_BARRIER_BIT 0x0100

#define	ERBAR_RXBARR_MASK 0xffff0000

#define	ERBAR_RXBARR_SHIFT 16

#define	ERCIR_RXCONSUME_MASK 0x00000fff

#define	ERPIR_RXPRODUCE_MASK 0x00000fff

#define	ERPIR_ARM 0x80000000

#define	ERTR_CNT_MASK 0x000007ff

#define	ETCSR_IPGT_MASK 0x0000007f

#define	ETCSR_IPGR1_MASK 0x00007f00

#define	ETCSR_IPGR1_SHIFT 8

#define	ETCSR_IPGR2_MASK 0x007f0000

#define	ETCSR_IPGR2_SHIFT 16

#define	ETCSR_NOTXCLK 0x80000000

#define	ETCDC_COLLCNT_MASK 0x0000ffff

#define	ETCDC_DEFERCNT_MASK 0xffff0000

#define	ETCDC_DEFERCNT_SHIFT 16

#define	ETBR_ALIGNMENT (64*1024)

#define	ETBR_L_RINGSZ_MASK 0x00000001

#define	ETBR_L_RINGSZ128 0

#define	ETBR_L_RINGSZ512 1

#define	ETBR_L_TXRINGBASE_MASK 0xffffc000

#define	ETCIR_TXCONSUME_MASK 0x0000ffff

#define	ETCIR_IDLE 0x80000000

#define	ETPIR_TXPRODUCE_MASK 0x0000ffff

#define	EBIR_TXBUFPROD_MASK 0x0000001f

#define	EBIR_TXBUFCONS_MASK 0x00001f00

#define	EBIR_TXBUFCONS_SHIFT 8

#define	EBIR_RXBUFPROD_MASK 0x007fc000

#define	EBIR_RXBUFPROD_SHIFT 14

#define	EBIR_RXBUFCONS_MASK 0xff800000

#define	EBIR_RXBUFCONS_SHIFT 23

#define	MICR_REGADDR_MASK 0x0000001f

#define	MICR_PHYADDR_MASK 0x000003e0

#define	MICR_PHYADDR_SHIFT 5

#define	MICR_READTRIG 0x00000400

#define	MICR_BUSY 0x00000800

#define	MIDR_DATA_MASK 0x0000ffff

#define	ERXBUF_IPCKSUM_MASK 0x0000ffff

#define	ERXBUF_BYTECNT_MASK 0x07ff0000

#define	ERXBUF_BYTECNT_SHIFT 16

#define	ERXBUF_V 0x80000000

#define	ERXBUF_CRCERR 0x00000001 /* aka RSV15 */

#define	ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */

#define	ERXBUF_CODERR 0x00000004 /* aka RSV13 */

#define	ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */

#define	ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */

#define	ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */

#define	ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */

#define	ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */

#define	ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */

#define	ERXBUF_BADPKT 0x20000000 /* aka RSV20 */

#define	ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */

#define	ERXBUF_CARRIER 0x80000000 /* aka RSV22 */

#define	ETXD_BYTECNT_MASK 0x000007ff /* total byte count */

#define	ETXD_INTWHENDONE 0x00001000 /* intr when done */

#define	ETXD_D0V 0x00010000 /* data 0 valid */

#define	ETXD_B1V 0x00020000 /* buf 1 valid */

#define	ETXD_B2V 0x00040000 /* buf 2 valid */

#define	ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */

#define	ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */

#define	ETXD_CHKOFF_SHIFT 20

#define	ETXD_D0CNT_MASK 0x0000007f

#define	ETXD_B1CNT_MASK 0x0007ff00

#define	ETXD_B1CNT_SHIFT 8

#define	ETXD_B2CNT_MASK 0x7ff00000

#define	ETXD_B2CNT_SHIFT 20

#define	IOC3_SDB_ETHER (1<<ioc3_subdev_ether)

#define	IOC3_SDB_GENERIC (1<<ioc3_subdev_generic)

#define	IOC3_SDB_NIC (1<<ioc3_subdev_nic)

#define	IOC3_SDB_KBMS (1<<ioc3_subdev_kbms)

#define	IOC3_SDB_TTYA (1<<ioc3_subdev_ttya)

#define	IOC3_SDB_TTYB (1<<ioc3_subdev_ttyb)

#define	IOC3_SDB_ECPP (1<<ioc3_subdev_ecpp)

#define	IOC3_SDB_RT (1<<ioc3_subdev_rt)

#define	IOC3_ALL_SUBDEVS ((1<<ioc3_nsubdevs)-1)

#define	IOC3_SDB_SERIAL (IOC3_SDB_TTYA\|IOC3_SDB_TTYB)

#define	IOC3_STD_SUBDEVS IOC3_ALL_SUBDEVS

#define	IOC3_INTA_SUBDEVS IOC3_SDB_ETHER

#define	IOC3_INTB_SUBDEVS (IOC3_SDB_GENERIC\|IOC3_SDB_KBMS\|IOC3_SDB_SERIAL\|IOC3_SDB_ECPP\|IOC3_SDB_RT)

Typedefs
typedef struct ioc3_uartregs	ioc3_uregs_t

typedef enum ioc3_subdevs_e	ioc3_subdev_t

Enumerations
enum	ioc3_subdevs_e { ioc3_subdev_ether, ioc3_subdev_generic, ioc3_subdev_nic, ioc3_subdev_kbms, ioc3_subdev_ttya, ioc3_subdev_ttyb, ioc3_subdev_ecpp, ioc3_subdev_rt, ioc3_nsubdevs }

Macro Definition Documentation

#define EBIR_RXBUFCONS_MASK 0xff800000

Definition at line 584 of file ioc3.h.

#define EBIR_RXBUFCONS_SHIFT 23

Definition at line 585 of file ioc3.h.

#define EBIR_RXBUFPROD_MASK 0x007fc000

Definition at line 582 of file ioc3.h.

#define EBIR_RXBUFPROD_SHIFT 14

Definition at line 583 of file ioc3.h.

#define EBIR_TXBUFCONS_MASK 0x00001f00

Definition at line 580 of file ioc3.h.

#define EBIR_TXBUFCONS_SHIFT 8

Definition at line 581 of file ioc3.h.

#define EBIR_TXBUFPROD_MASK 0x0000001f

Definition at line 579 of file ioc3.h.

#define EISR_RXBUFOFLO 0x00000008

Definition at line 524 of file ioc3.h.

#define EISR_RXMEMERR 0x00000010

Definition at line 525 of file ioc3.h.

#define EISR_RXOFLO 0x00000004

Definition at line 523 of file ioc3.h.

#define EISR_RXPARERR 0x00000020

Definition at line 526 of file ioc3.h.

#define EISR_RXTHRESHINT 0x00000002

Definition at line 522 of file ioc3.h.

#define EISR_RXTIMERINT 0x00000001

Definition at line 521 of file ioc3.h.

#define EISR_TXBUFUFLO 0x00200000

Definition at line 532 of file ioc3.h.

#define EISR_TXCOLLWRAP 0x00800000

Definition at line 534 of file ioc3.h.

#define EISR_TXDEFERWRAP 0x01000000

Definition at line 535 of file ioc3.h.

#define EISR_TXEMPTY 0x00010000

Definition at line 527 of file ioc3.h.

#define EISR_TXEXDEF 0x00040000

Definition at line 529 of file ioc3.h.

#define EISR_TXEXPLICIT 0x00400000

Definition at line 533 of file ioc3.h.

#define EISR_TXGIANT 0x00100000

Definition at line 531 of file ioc3.h.

#define EISR_TXLCOL 0x00080000

Definition at line 530 of file ioc3.h.

#define EISR_TXMEMERR 0x02000000

Definition at line 536 of file ioc3.h.

#define EISR_TXPARERR 0x04000000

Definition at line 537 of file ioc3.h.

#define EISR_TXRTRY 0x00020000

Definition at line 528 of file ioc3.h.

#define EMCR_ARB_DIAG 0x001c0000

Definition at line 517 of file ioc3.h.

#define EMCR_ARB_DIAG_IDLE 0x00200000

Definition at line 518 of file ioc3.h.

#define EMCR_BADPAR 0x00000800

Definition at line 510 of file ioc3.h.

#define EMCR_BUFSIZ 0x00001000

Definition at line 511 of file ioc3.h.

#define EMCR_DUPLEX 0x00000001

Definition at line 504 of file ioc3.h.

#define EMCR_LOOPBACK 0x00020000

Definition at line 516 of file ioc3.h.

#define EMCR_PADEN 0x00000004

Definition at line 506 of file ioc3.h.

#define EMCR_PROMISC 0x00000002

Definition at line 505 of file ioc3.h.

#define EMCR_RAMPAR 0x00000200

Definition at line 509 of file ioc3.h.

#define EMCR_RST 0x80000000

Definition at line 519 of file ioc3.h.

#define EMCR_RXDMAEN 0x00008000

Definition at line 514 of file ioc3.h.

#define EMCR_RXEN 0x00010000

Definition at line 515 of file ioc3.h.

#define EMCR_RXOFF_MASK 0x000001f8

Definition at line 507 of file ioc3.h.

#define EMCR_RXOFF_SHIFT 3

Definition at line 508 of file ioc3.h.

#define EMCR_TXDMAEN 0x00002000

Definition at line 512 of file ioc3.h.

#define EMCR_TXEN 0x00004000

Definition at line 513 of file ioc3.h.

#define ERBAR_BARRIER_BIT 0x0100

Definition at line 546 of file ioc3.h.

#define ERBAR_RXBARR_MASK 0xffff0000

Definition at line 547 of file ioc3.h.

#define ERBAR_RXBARR_SHIFT 16

Definition at line 548 of file ioc3.h.

#define ERBR_ALIGNMENT 4096

Definition at line 543 of file ioc3.h.

#define ERBR_L_RXRINGBASE_MASK 0xfffff000

Definition at line 544 of file ioc3.h.

#define ERCIR_RXCONSUME_MASK 0x00000fff

Definition at line 550 of file ioc3.h.

#define ERCSR_DIAG_OFLO 0x80000000 /* simulation only */

Definition at line 541 of file ioc3.h.

#define ERCSR_RX_TMR 0x40000000 /* simulation only */

Definition at line 540 of file ioc3.h.

#define ERCSR_THRESH_MASK 0x000001ff /* enet RX threshold */

Definition at line 539 of file ioc3.h.

#define ERPIR_ARM 0x80000000

Definition at line 553 of file ioc3.h.

#define ERPIR_RXPRODUCE_MASK 0x00000fff

Definition at line 552 of file ioc3.h.

#define ERTR_CNT_MASK 0x000007ff

Definition at line 555 of file ioc3.h.

#define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */

Definition at line 609 of file ioc3.h.

#define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */

Definition at line 609 of file ioc3.h.

#define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */

Definition at line 607 of file ioc3.h.

#define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */

Definition at line 607 of file ioc3.h.

#define ERXBUF_BYTECNT_MASK 0x07ff0000

Definition at line 596 of file ioc3.h.

#define ERXBUF_BYTECNT_MASK 0x07ff0000

Definition at line 596 of file ioc3.h.

#define ERXBUF_BYTECNT_SHIFT 16

Definition at line 597 of file ioc3.h.

#define ERXBUF_BYTECNT_SHIFT 16

Definition at line 597 of file ioc3.h.

#define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */

Definition at line 611 of file ioc3.h.

#define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */

Definition at line 611 of file ioc3.h.

#define ERXBUF_CODERR 0x00000004 /* aka RSV13 */

Definition at line 602 of file ioc3.h.

#define ERXBUF_CODERR 0x00000004 /* aka RSV13 */

Definition at line 602 of file ioc3.h.

#define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */

Definition at line 600 of file ioc3.h.

#define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */

Definition at line 600 of file ioc3.h.

#define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */

Definition at line 601 of file ioc3.h.

#define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */

Definition at line 601 of file ioc3.h.

#define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */

Definition at line 610 of file ioc3.h.

#define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */

Definition at line 610 of file ioc3.h.

#define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */

Definition at line 605 of file ioc3.h.

#define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */

Definition at line 605 of file ioc3.h.

#define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */

Definition at line 603 of file ioc3.h.

#define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */

Definition at line 603 of file ioc3.h.

#define ERXBUF_IPCKSUM_MASK 0x0000ffff

Definition at line 595 of file ioc3.h.

#define ERXBUF_IPCKSUM_MASK 0x0000ffff

Definition at line 595 of file ioc3.h.

#define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */

Definition at line 604 of file ioc3.h.

#define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */

Definition at line 604 of file ioc3.h.

#define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */

Definition at line 608 of file ioc3.h.

#define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */

Definition at line 608 of file ioc3.h.

#define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */

Definition at line 606 of file ioc3.h.

#define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */

Definition at line 606 of file ioc3.h.

#define ERXBUF_V 0x80000000

Definition at line 598 of file ioc3.h.

#define ERXBUF_V 0x80000000

Definition at line 598 of file ioc3.h.

#define ETBR_ALIGNMENT (64*1024)

Definition at line 568 of file ioc3.h.

#define ETBR_L_RINGSZ128 0

Definition at line 570 of file ioc3.h.

#define ETBR_L_RINGSZ512 1

Definition at line 571 of file ioc3.h.

#define ETBR_L_RINGSZ_MASK 0x00000001

Definition at line 569 of file ioc3.h.

#define ETBR_L_TXRINGBASE_MASK 0xffffc000

Definition at line 572 of file ioc3.h.

#define ETCDC_COLLCNT_MASK 0x0000ffff

Definition at line 564 of file ioc3.h.

#define ETCDC_DEFERCNT_MASK 0xffff0000

Definition at line 565 of file ioc3.h.

#define ETCDC_DEFERCNT_SHIFT 16

Definition at line 566 of file ioc3.h.

#define ETCIR_IDLE 0x80000000

Definition at line 575 of file ioc3.h.

#define ETCIR_TXCONSUME_MASK 0x0000ffff

Definition at line 574 of file ioc3.h.

#define ETCSR_IPGR1_MASK 0x00007f00

Definition at line 558 of file ioc3.h.

#define ETCSR_IPGR1_SHIFT 8

Definition at line 559 of file ioc3.h.

#define ETCSR_IPGR2_MASK 0x007f0000

Definition at line 560 of file ioc3.h.

#define ETCSR_IPGR2_SHIFT 16

Definition at line 561 of file ioc3.h.

#define ETCSR_IPGT_MASK 0x0000007f

Definition at line 557 of file ioc3.h.

#define ETCSR_NOTXCLK 0x80000000

Definition at line 562 of file ioc3.h.

#define ETPIR_TXPRODUCE_MASK 0x0000ffff

Definition at line 577 of file ioc3.h.

#define ETXD_B1CNT_MASK 0x0007ff00

Definition at line 623 of file ioc3.h.

#define ETXD_B1CNT_MASK 0x0007ff00

Definition at line 623 of file ioc3.h.

#define ETXD_B1CNT_SHIFT 8

Definition at line 624 of file ioc3.h.

#define ETXD_B1CNT_SHIFT 8

Definition at line 624 of file ioc3.h.

#define ETXD_B1V 0x00020000 /* buf 1 valid */

Definition at line 616 of file ioc3.h.

#define ETXD_B1V 0x00020000 /* buf 1 valid */

Definition at line 616 of file ioc3.h.

#define ETXD_B2CNT_MASK 0x7ff00000

Definition at line 625 of file ioc3.h.

#define ETXD_B2CNT_MASK 0x7ff00000

Definition at line 625 of file ioc3.h.

#define ETXD_B2CNT_SHIFT 20

Definition at line 626 of file ioc3.h.

#define ETXD_B2CNT_SHIFT 20

Definition at line 626 of file ioc3.h.

#define ETXD_B2V 0x00040000 /* buf 2 valid */

Definition at line 617 of file ioc3.h.

#define ETXD_B2V 0x00040000 /* buf 2 valid */

Definition at line 617 of file ioc3.h.

#define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */

Definition at line 613 of file ioc3.h.

#define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */

Definition at line 613 of file ioc3.h.

#define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */

Definition at line 619 of file ioc3.h.

#define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */

Definition at line 619 of file ioc3.h.

#define ETXD_CHKOFF_SHIFT 20

Definition at line 620 of file ioc3.h.

#define ETXD_CHKOFF_SHIFT 20

Definition at line 620 of file ioc3.h.

#define ETXD_D0CNT_MASK 0x0000007f

Definition at line 622 of file ioc3.h.

#define ETXD_D0CNT_MASK 0x0000007f

Definition at line 622 of file ioc3.h.

#define ETXD_D0V 0x00010000 /* data 0 valid */

Definition at line 615 of file ioc3.h.

#define ETXD_D0V 0x00010000 /* data 0 valid */

Definition at line 615 of file ioc3.h.

#define ETXD_DATALEN 104

Definition at line 211 of file ioc3.h.

#define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */

Definition at line 618 of file ioc3.h.

#define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */

Definition at line 618 of file ioc3.h.

#define ETXD_INTWHENDONE 0x00001000 /* intr when done */

Definition at line 614 of file ioc3.h.

#define ETXD_INTWHENDONE 0x00001000 /* intr when done */

Definition at line 614 of file ioc3.h.

#define GPCR_DIR 0x000000ff /* tristate pin input or output */

Definition at line 483 of file ioc3.h.

#define GPCR_DIR_PHY_RST 0x00000020 /* ethernet PHY reset enable */

Definition at line 493 of file ioc3.h.

#define GPCR_DIR_PIN ( x ) (1<<(x)) /* access one of the DIR bits */

Definition at line 484 of file ioc3.h.

#define GPCR_DIR_SERA_XCVR 0x00000080 /* Port A Transceiver select enable */

Definition at line 491 of file ioc3.h.

#define GPCR_DIR_SERB_XCVR 0x00000040 /* Port B Transceiver select enable */

Definition at line 492 of file ioc3.h.

#define GPCR_EDGE 0x000f0000 /* extint edge or level sensitive */

Definition at line 485 of file ioc3.h.

#define GPCR_EDGE_PIN ( x ) (1<<((x)+15)) /* access one of the EDGE bits */

Definition at line 486 of file ioc3.h.

#define GPCR_INT_OUT_EN 0x00100000 /* enable INT_OUT to pin 0 */

Definition at line 489 of file ioc3.h.

#define GPCR_MLAN_EN 0x00200000 /* enable MCR to pin 8 */

Definition at line 490 of file ioc3.h.

#define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */

Definition at line 496 of file ioc3.h.

#define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */

Definition at line 498 of file ioc3.h.

#define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */

Definition at line 497 of file ioc3.h.

#define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */

Definition at line 500 of file ioc3.h.

#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin controlling uart a mode select */

Definition at line 502 of file ioc3.h.

#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin controlling uart b mode select */

Definition at line 501 of file ioc3.h.

#define INT_OUT_COUNT 0x0000ffff /* pulse interval timer */

Definition at line 461 of file ioc3.h.

#define INT_OUT_COUNT_TO_US ( x )

Value:

/* convert count value to uS */ \

(((x) + 1) * INT_OUT_NS_PER_TICK / 1000)

Definition at line 477 of file ioc3.h.

#define INT_OUT_DIAG 0x40000000 /* diag mode */

Definition at line 468 of file ioc3.h.

#define INT_OUT_INT_OUT 0x80000000 /* current state of INT_OUT */

Definition at line 469 of file ioc3.h.

#define INT_OUT_MAX_TICKS INT_OUT_COUNT /* largest possible count */

Definition at line 480 of file ioc3.h.

#define INT_OUT_MIN_TICKS 3 /* min period is width of pulse in "ticks" */

Definition at line 479 of file ioc3.h.

#define INT_OUT_MODE 0x00070000 /* mode mask */

Definition at line 462 of file ioc3.h.

#define INT_OUT_MODE_0 0x00000000 /* set output to 0 */

Definition at line 463 of file ioc3.h.

#define INT_OUT_MODE_1 0x00040000 /* set output to 1 */

Definition at line 464 of file ioc3.h.

#define INT_OUT_MODE_1PULSE 0x00050000 /* send 1 pulse */

Definition at line 465 of file ioc3.h.

#define INT_OUT_MODE_PULSES 0x00060000 /* send 1 pulse every interval */

Definition at line 466 of file ioc3.h.

#define INT_OUT_MODE_SQW 0x00070000 /* toggle output every interval */

Definition at line 467 of file ioc3.h.

#define INT_OUT_NS_PER_TICK (30 * 260) /* 30 ns PCI clock, divisor=260 */

Definition at line 472 of file ioc3.h.

#define INT_OUT_TICKS_PER_PULSE 3 /* outgoing pulse lasts 3 ticks */

Definition at line 473 of file ioc3.h.

#define INT_OUT_US_TO_COUNT ( x )

Value:

/* convert uS to a count value */ \
    (((x) * 10 + INT_OUT_NS_PER_TICK / 200) *   \
     100 / INT_OUT_NS_PER_TICK - 1)

Definition at line 474 of file ioc3.h.

#define IOC3_ALL_SUBDEVS ((1<<ioc3_nsubdevs)-1)

Definition at line 652 of file ioc3.h.

#define IOC3_BYTEBUS_DEV0 0x80000L

Definition at line 238 of file ioc3.h.

#define IOC3_BYTEBUS_DEV1 0xa0000L

Definition at line 239 of file ioc3.h.

#define IOC3_BYTEBUS_DEV2 0xc0000L

Definition at line 240 of file ioc3.h.

#define IOC3_BYTEBUS_DEV3 0xe0000L

Definition at line 241 of file ioc3.h.

#define IOC3_INTA_SUBDEVS IOC3_SDB_ETHER

Definition at line 658 of file ioc3.h.

#define IOC3_INTB_SUBDEVS (IOC3_SDB_GENERIC|IOC3_SDB_KBMS|IOC3_SDB_SERIAL|IOC3_SDB_ECPP|IOC3_SDB_RT)

Definition at line 659 of file ioc3.h.

#define IOC3_PENDING_INTRS ( mem )

Value:

(PCI_INW(&((mem)->sio_ir)) & \

PCI_INW(&((mem)->sio_ies_ro)))

Definition at line 441 of file ioc3.h.

#define IOC3_SDB_ECPP (1<<ioc3_subdev_ecpp)

Definition at line 649 of file ioc3.h.

#define IOC3_SDB_ETHER (1<<ioc3_subdev_ether)

Definition at line 643 of file ioc3.h.

#define IOC3_SDB_GENERIC (1<<ioc3_subdev_generic)

Definition at line 644 of file ioc3.h.

#define IOC3_SDB_KBMS (1<<ioc3_subdev_kbms)

Definition at line 646 of file ioc3.h.

#define IOC3_SDB_NIC (1<<ioc3_subdev_nic)

Definition at line 645 of file ioc3.h.

#define IOC3_SDB_RT (1<<ioc3_subdev_rt)

Definition at line 650 of file ioc3.h.

#define IOC3_SDB_SERIAL (IOC3_SDB_TTYA|IOC3_SDB_TTYB)

Definition at line 654 of file ioc3.h.

#define IOC3_SDB_TTYA (1<<ioc3_subdev_ttya)

Definition at line 647 of file ioc3.h.

#define IOC3_SDB_TTYB (1<<ioc3_subdev_ttyb)

Definition at line 648 of file ioc3.h.

#define IOC3_SIO_BASE 0x20000

Definition at line 246 of file ioc3.h.

#define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142) /* KBD Config */

Definition at line 248 of file ioc3.h.

#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */

Definition at line 249 of file ioc3.h.

#define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168) /* Real Time Clock */

Definition at line 250 of file ioc3.h.

#define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE) /* UART A */

Definition at line 252 of file ioc3.h.

#define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141) /* UART Config */

Definition at line 247 of file ioc3.h.

#define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE) /* UART B */

Definition at line 251 of file ioc3.h.

#define IOC3_SSRAM IOC3_RAM_OFF /* base of SSRAM diagnostic access */

Definition at line 255 of file ioc3.h.

#define IOC3_SSRAM_DM 0x0000ffff /* data mask */

Definition at line 257 of file ioc3.h.

#define IOC3_SSRAM_LEN 0x40000 /* 256kb (address space size, may not be fully populated) */

Definition at line 256 of file ioc3.h.

#define IOC3_SSRAM_PM 0x00010000 /* parity mask */

Definition at line 258 of file ioc3.h.

#define IOC3_STD_SUBDEVS IOC3_ALL_SUBDEVS

Definition at line 656 of file ioc3.h.

#define iu_dll u1.dll

Definition at line 34 of file ioc3.h.

#define iu_dlm u2.dlm

Definition at line 36 of file ioc3.h.

#define iu_fcr u3.fcr

Definition at line 38 of file ioc3.h.

#define iu_ier u2.ier

Definition at line 35 of file ioc3.h.

#define iu_iir u3.iir

Definition at line 37 of file ioc3.h.

#define iu_rbr u1.rbr

Definition at line 32 of file ioc3.h.

#define iu_thr u1.thr

Definition at line 33 of file ioc3.h.

#define KM_CSR_EMM_MODE 0x00001000 /* emulation mode */

Definition at line 286 of file ioc3.h.

#define KM_CSR_K_CLAMP_ONE 0x00100000 /* Pull K_CLK low after rec. one char */

Definition at line 294 of file ioc3.h.

#define KM_CSR_K_CLAMP_THREE 0x00400000 /* Pull K_CLK low after rec. three chars */

Definition at line 296 of file ioc3.h.

#define KM_CSR_K_CLK 0x00000020 /* state of kbd clock line */

Definition at line 279 of file ioc3.h.

#define KM_CSR_K_DATA 0x00000010 /* state of kbd data line */

Definition at line 278 of file ioc3.h.

#define KM_CSR_K_LCB 0x00000004 /* Line Cntrl Bit for last KBD write */

Definition at line 276 of file ioc3.h.

#define KM_CSR_K_PULL_CLK 0x00000080 /* pull kbd clock line low */

Definition at line 281 of file ioc3.h.

#define KM_CSR_K_PULL_DATA 0x00000040 /* pull kbd data line low */

Definition at line 280 of file ioc3.h.

#define KM_CSR_K_SM_IDLE 0x00004000 /* Keyboard is idle */

Definition at line 288 of file ioc3.h.

#define KM_CSR_K_TO 0x00010000 /* Keyboard trying to send/receive */

Definition at line 290 of file ioc3.h.

#define KM_CSR_K_TO_EN

Value:

0x00040000 /* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause

SIO_IR to assert */

Definition at line 292 of file ioc3.h.

#define KM_CSR_K_WRT_PEND 0x00000001 /* kbd port xmitting or resetting */

Definition at line 274 of file ioc3.h.

#define KM_CSR_M_CLAMP_ONE 0x00200000 /* Pull M_CLK low after rec. one char */

Definition at line 295 of file ioc3.h.

#define KM_CSR_M_CLAMP_THREE 0x00800000 /* Pull M_CLK low after rec. three char */

Definition at line 297 of file ioc3.h.

#define KM_CSR_M_CLK 0x00000200 /* state of ms clock line */

Definition at line 283 of file ioc3.h.

#define KM_CSR_M_DATA 0x00000100 /* state of ms data line */

Definition at line 282 of file ioc3.h.

#define KM_CSR_M_LCB 0x00000008 /* same for mouse */

Definition at line 277 of file ioc3.h.

#define KM_CSR_M_PULL_CLK 0x00000800 /* pull ms clock line low */

Definition at line 285 of file ioc3.h.

#define KM_CSR_M_PULL_DATA 0x00000400 /* pull ms data line low */

Definition at line 284 of file ioc3.h.

#define KM_CSR_M_SM_IDLE 0x00008000 /* Mouse is idle */

Definition at line 289 of file ioc3.h.

#define KM_CSR_M_TO 0x00020000 /* Mouse trying to send/receive */

Definition at line 291 of file ioc3.h.

#define KM_CSR_M_TO_EN

Value:

0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause

SIO_IR to assert */

Definition at line 293 of file ioc3.h.

#define KM_CSR_M_WRT_PEND 0x00000002 /* mouse port xmitting or resetting */

Definition at line 275 of file ioc3.h.

#define KM_CSR_SIM_MODE 0x00002000 /* clock X8 */

Definition at line 287 of file ioc3.h.

#define KM_RD_DATA_0 0x00ff0000 /* 1st char recvd since last read */

Definition at line 304 of file ioc3.h.

#define KM_RD_DATA_0_SHIFT 16

Definition at line 305 of file ioc3.h.

#define KM_RD_DATA_1 0x0000ff00 /* 2nd char recvd since last read */

Definition at line 302 of file ioc3.h.

#define KM_RD_DATA_1_SHIFT 8

Definition at line 303 of file ioc3.h.

#define KM_RD_DATA_2 0x000000ff /* 3rd char recvd since last read */

Definition at line 300 of file ioc3.h.

#define KM_RD_DATA_2_SHIFT 0

Definition at line 301 of file ioc3.h.

#define KM_RD_FRAME_ERR_0 0x04000000 /* same for byte 0 */

Definition at line 308 of file ioc3.h.

#define KM_RD_FRAME_ERR_1 0x02000000 /* same for byte 1 */

Definition at line 307 of file ioc3.h.

#define KM_RD_FRAME_ERR_2 0x01000000 /* framing or parity error in byte 2 */

Definition at line 306 of file ioc3.h.

#define KM_RD_KBD_MSE 0x08000000 /* 0 if from kbd, 1 if from mouse */

Definition at line 310 of file ioc3.h.

#define KM_RD_OFLO 0x10000000 /* 4th char recvd before this read */

Definition at line 311 of file ioc3.h.

#define KM_RD_VALID_0 0x80000000 /* DATA_0 valid */

Definition at line 314 of file ioc3.h.

#define KM_RD_VALID_1 0x40000000 /* DATA_1 valid */

Definition at line 313 of file ioc3.h.

#define KM_RD_VALID_2 0x20000000 /* DATA_2 valid */

Definition at line 312 of file ioc3.h.

#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2)

Definition at line 315 of file ioc3.h.

#define KM_WD_WRT_DATA 0x000000ff /* write to keyboard/mouse port */

Definition at line 318 of file ioc3.h.

#define KM_WD_WRT_DATA_SHIFT 0

Definition at line 319 of file ioc3.h.

#define MICR_BUSY 0x00000800

Definition at line 591 of file ioc3.h.

#define MICR_PHYADDR_MASK 0x000003e0

Definition at line 588 of file ioc3.h.

#define MICR_PHYADDR_SHIFT 5

Definition at line 589 of file ioc3.h.

#define MICR_READTRIG 0x00000400

Definition at line 590 of file ioc3.h.

#define MICR_REGADDR_MASK 0x0000001f

Definition at line 587 of file ioc3.h.

#define MIDR_DATA_MASK 0x0000ffff

Definition at line 593 of file ioc3.h.

#define PCI_SCR_DROP_MODE (0x1 << 17)

Definition at line 265 of file ioc3.h.

#define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */

Definition at line 263 of file ioc3.h.

#define PCI_SCR_PAR_ERR (0x1 << 31)

Definition at line 271 of file ioc3.h.

#define PCI_SCR_PAR_RESP_EN 0x00000040 /* enb PCI parity checking */

Definition at line 261 of file ioc3.h.

#define PCI_SCR_RX_SERR (0x1 << 16)

Definition at line 264 of file ioc3.h.

#define PCI_SCR_RX_TAR_ABRT (0x1 << 28)

Definition at line 268 of file ioc3.h.

#define PCI_SCR_SERR_EN 0x00000100 /* enable the SERR# driver */

Definition at line 262 of file ioc3.h.

#define PCI_SCR_SIG_MST_ABRT (0x1 << 29)

Definition at line 269 of file ioc3.h.

#define PCI_SCR_SIG_PAR_ERR (0x1 << 24)

Definition at line 266 of file ioc3.h.

#define PCI_SCR_SIG_SERR (0x1 << 30)

Definition at line 270 of file ioc3.h.

#define PCI_SCR_SIG_TAR_ABRT (0x1 << 27)

Definition at line 267 of file ioc3.h.

#define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */

Definition at line 358 of file ioc3.h.

#define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */

Definition at line 357 of file ioc3.h.

#define PROD_CONS_PTR_OFF 3

Definition at line 359 of file ioc3.h.

#define RXSB_BREAK 0x08 /* break character */

Definition at line 325 of file ioc3.h.

#define RXSB_CTS 0x10 /* state of CTS */

Definition at line 326 of file ioc3.h.

#define RXSB_DATA_VALID 0x80 /* data byte, FRAME_ERR PAR_ERR & BREAK valid */

Definition at line 329 of file ioc3.h.

#define RXSB_DCD 0x20 /* state of DCD */

Definition at line 327 of file ioc3.h.

#define RXSB_FRAME_ERR 0x04 /* framing error */

Definition at line 324 of file ioc3.h.

#define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */

Definition at line 328 of file ioc3.h.

#define RXSB_OVERRUN 0x01 /* char(s) lost */

Definition at line 322 of file ioc3.h.

#define RXSB_PAR_ERR 0x02 /* parity error */

Definition at line 323 of file ioc3.h.

#define SBBR_L_BASE 0xfffff000 /* lower serial ring base addr */

Definition at line 340 of file ioc3.h.

#define SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */

Definition at line 339 of file ioc3.h.

#define SHADOW_BI 0x00000010 /* break interrupt */

Definition at line 377 of file ioc3.h.

#define SHADOW_CTS 0x00100000 /* clear to send */

Definition at line 383 of file ioc3.h.

#define SHADOW_DCD 0x00800000 /* data carrier detect */

Definition at line 384 of file ioc3.h.

#define SHADOW_DCTS 0x00010000 /* delta clear to send */

Definition at line 381 of file ioc3.h.

#define SHADOW_DDCD 0x00080000 /* delta data carrier detect */

Definition at line 382 of file ioc3.h.

#define SHADOW_DR 0x00000001 /* data ready */

Definition at line 373 of file ioc3.h.

#define SHADOW_DTR 0x01000000 /* data terminal ready */

Definition at line 385 of file ioc3.h.

#define SHADOW_FE 0x00000008 /* framing error */

Definition at line 376 of file ioc3.h.

#define SHADOW_LOOP 0x10000000 /* loopback enabled */

Definition at line 389 of file ioc3.h.

#define SHADOW_OE 0x00000002 /* overrun error */

Definition at line 374 of file ioc3.h.

#define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */

Definition at line 387 of file ioc3.h.

#define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */

Definition at line 388 of file ioc3.h.

#define SHADOW_PE 0x00000004 /* parity error */

Definition at line 375 of file ioc3.h.

#define SHADOW_RFCE 0x00000080 /* char in RX fifo has an error */

Definition at line 380 of file ioc3.h.

#define SHADOW_RTS 0x02000000 /* request to send */

Definition at line 386 of file ioc3.h.

#define SHADOW_TEMT 0x00000040 /* transmit shift register empty */

Definition at line 379 of file ioc3.h.

#define SHADOW_THRE 0x00000020 /* transmit holding register empty */

Definition at line 378 of file ioc3.h.

#define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */

Definition at line 452 of file ioc3.h.

#define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */

Definition at line 458 of file ioc3.h.

#define SIO_CR_ARB_DIAG_PP 0x00200000

Definition at line 457 of file ioc3.h.

#define SIO_CR_ARB_DIAG_RXA 0x00080000

Definition at line 454 of file ioc3.h.

#define SIO_CR_ARB_DIAG_RXB 0x00180000

Definition at line 456 of file ioc3.h.

#define SIO_CR_ARB_DIAG_TXA 0x00000000

Definition at line 453 of file ioc3.h.

#define SIO_CR_ARB_DIAG_TXB 0x00100000

Definition at line 455 of file ioc3.h.

#define SIO_CR_CMD_PULSE_SHIFT 15

Definition at line 451 of file ioc3.h.

#define SIO_CR_SER_A_BASE 0x000000fe /* DMA poll addr port A */

Definition at line 446 of file ioc3.h.

#define SIO_CR_SER_A_BASE_SHIFT 1

Definition at line 447 of file ioc3.h.

#define SIO_CR_SER_B_BASE 0x00007f00 /* DMA poll addr port B */

Definition at line 448 of file ioc3.h.

#define SIO_CR_SER_B_BASE_SHIFT 8

Definition at line 449 of file ioc3.h.

#define SIO_CR_SIO_RESET 0x00000001 /* reset the SIO */

Definition at line 445 of file ioc3.h.

#define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */

Definition at line 422 of file ioc3.h.

#define SIO_IR_GEN_INT_SHIFT 28

Definition at line 423 of file ioc3.h.

#define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */

Definition at line 420 of file ioc3.h.

#define SIO_IR_PP

Value:

(SIO_IR_PP_INT | SIO_IR_PP_INTA | \

SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)

Definition at line 436 of file ioc3.h.

#define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */

Definition at line 416 of file ioc3.h.

#define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */

Definition at line 417 of file ioc3.h.

#define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */

Definition at line 418 of file ioc3.h.

#define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */

Definition at line 419 of file ioc3.h.

#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1)

Definition at line 438 of file ioc3.h.

#define SIO_IR_RT_INT 0x08000000 /* RT output pulse */

Definition at line 421 of file ioc3.h.

#define SIO_IR_SA

Value:

(SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \
                 SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \
                 SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \
                 SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \
                 SIO_IR_SA_MEMERR)

Definition at line 426 of file ioc3.h.

#define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */

Definition at line 403 of file ioc3.h.

#define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */

Definition at line 402 of file ioc3.h.

#define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */

Definition at line 404 of file ioc3.h.

#define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */

Definition at line 406 of file ioc3.h.

#define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */

Definition at line 399 of file ioc3.h.

#define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */

Definition at line 400 of file ioc3.h.

#define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */

Definition at line 401 of file ioc3.h.

#define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */

Definition at line 405 of file ioc3.h.

#define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */

Definition at line 398 of file ioc3.h.

#define SIO_IR_SB

Value:

(SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \
                 SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \
                 SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \
                 SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \
                 SIO_IR_SB_MEMERR)

Definition at line 431 of file ioc3.h.

#define SIO_IR_SB_DELTA_CTS 0x00004000 /* */

Definition at line 412 of file ioc3.h.

#define SIO_IR_SB_DELTA_DCD 0x00002000 /* */

Definition at line 411 of file ioc3.h.

#define SIO_IR_SB_INT 0x00008000 /* */

Definition at line 413 of file ioc3.h.

#define SIO_IR_SB_MEMERR 0x00020000 /* */

Definition at line 415 of file ioc3.h.

#define SIO_IR_SB_RX_FULL 0x00000400 /* */

Definition at line 408 of file ioc3.h.

#define SIO_IR_SB_RX_HIGH 0x00000800 /* */

Definition at line 409 of file ioc3.h.

#define SIO_IR_SB_RX_TIMER 0x00001000 /* */

Definition at line 410 of file ioc3.h.

#define SIO_IR_SB_TX_EXPLICIT 0x00010000 /* */

Definition at line 414 of file ioc3.h.

#define SIO_IR_SB_TX_MT 0x00000200 /* */

Definition at line 407 of file ioc3.h.

#define SIO_SR_CMD_PULSE 0x00078000 /* byte bus strobe length */

Definition at line 450 of file ioc3.h.

#define SRCIR_ARM 0x80000000 /* arm RX timer */

Definition at line 362 of file ioc3.h.

#define SRPIR_BYTE_CNT 0x07000000 /* bytes in packer */

Definition at line 365 of file ioc3.h.

#define SRPIR_BYTE_CNT_SHIFT 24

Definition at line 366 of file ioc3.h.

#define SRTR_CNT 0x00000fff /* reload value for RX timer */

Definition at line 392 of file ioc3.h.

#define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */

Definition at line 393 of file ioc3.h.

#define SRTR_CNT_VAL_SHIFT 16

Definition at line 394 of file ioc3.h.

#define SRTR_HZ 16000 /* SRTR clock frequency */

Definition at line 395 of file ioc3.h.

#define SSCR_DIAG 0x00200000 /* bypass clock divider for sim */

Definition at line 349 of file ioc3.h.

#define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */

Definition at line 351 of file ioc3.h.

#define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */

Definition at line 352 of file ioc3.h.

#define SSCR_HFC_EN 0x00020000 /* hardware flow control enabled */

Definition at line 345 of file ioc3.h.

#define SSCR_HIGH_SPD 0x00100000 /* 4X speed */

Definition at line 348 of file ioc3.h.

#define SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */

Definition at line 353 of file ioc3.h.

#define SSCR_RESET 0x80000000 /* reset DMA channels */

Definition at line 354 of file ioc3.h.

#define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */

Definition at line 350 of file ioc3.h.

#define SSCR_RX_RING_CTS 0x00080000 /* post RX record on delta-CTS */

Definition at line 347 of file ioc3.h.

#define SSCR_RX_RING_DCD 0x00040000 /* post RX record on delta-DCD */

Definition at line 346 of file ioc3.h.

#define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */

Definition at line 343 of file ioc3.h.

#define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */

Definition at line 344 of file ioc3.h.

#define STCIR_BYTE_CNT 0x0f000000 /* bytes in unpacker */

Definition at line 369 of file ioc3.h.

#define STCIR_BYTE_CNT_SHIFT 24

Definition at line 370 of file ioc3.h.

#define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */

Definition at line 336 of file ioc3.h.

#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */

Definition at line 332 of file ioc3.h.

#define TXCB_INVALID 0x00 /* byte is invalid */

Definition at line 333 of file ioc3.h.

#define TXCB_MCR 0x80 /* data<7:0> to modem control register */

Definition at line 335 of file ioc3.h.

#define TXCB_VALID 0x40 /* byte is valid */

Definition at line 334 of file ioc3.h.

Typedef Documentation

typedef enum ioc3_subdevs_e ioc3_subdev_t

typedef struct ioc3_uartregs ioc3_uregs_t

Enumeration Type Documentation

enum ioc3_subdevs_e

Enumerator:

ioc3_subdev_ether
ioc3_subdev_generic
ioc3_subdev_nic
ioc3_subdev_kbms
ioc3_subdev_ttya
ioc3_subdev_ttyb
ioc3_subdev_ecpp
ioc3_subdev_rt
ioc3_nsubdevs

Definition at line 628 of file ioc3.h.

Data Structures

Macros

Typedefs

Enumerations

Macro Definition Documentation

Typedef Documentation

Enumeration Type Documentation