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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | L1_CACHE_SHIFT 4 |
| #define | SH_CACHE_VALID 1 |
| #define | SH_CACHE_UPDATED 2 |
| #define | SH_CACHE_COMBINED 4 |
| #define | SH_CACHE_ASSOC 8 |
| #define | CCR 0xffffffec /* Address of Cache Control Register */ |
| #define | CCR_CACHE_CE 0x01 /* Cache Enable */ |
| #define | CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */ |
| #define | CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */ |
| #define | CCR_CACHE_CF 0x08 /* Cache Flush */ |
| #define | CCR_CACHE_ORA 0x20 /* RAM mode */ |
| #define | CACHE_OC_ADDRESS_ARRAY 0xf0000000 |
| #define | CACHE_PHYSADDR_MASK 0x1ffffc00 |
| #define | CCR_CACHE_ENABLE CCR_CACHE_CE |
| #define | CCR_CACHE_INVALIDATE CCR_CACHE_CF |
| #define CCR 0xffffffec /* Address of Cache Control Register */ |
| #define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */ |
| #define CCR_CACHE_ENABLE CCR_CACHE_CE |
| #define CCR_CACHE_INVALIDATE CCR_CACHE_CF |
| #define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */ |
1.8.2