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Linux Kernel
3.7.1
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Go to the source code of this file.
Macros | |
| #define | MMU_PTEH 0xFF000000 /* Page table entry register HIGH */ |
| #define | MMU_PTEL 0xFF000004 /* Page table entry register LOW */ |
| #define | MMU_TTB 0xFF000008 /* Translation table base register */ |
| #define | MMU_TEA 0xFF00000C /* TLB Exception Address */ |
| #define | MMU_PTEA 0xFF000034 /* PTE assistance register */ |
| #define | MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */ |
| #define | MMUCR 0xFF000010 /* MMU Control Register */ |
| #define | MMU_TLB_ENTRY_SHIFT 8 |
| #define | MMU_ITLB_ADDRESS_ARRAY 0xF2000000 |
| #define | MMU_ITLB_ADDRESS_ARRAY2 0xF2800000 |
| #define | MMU_ITLB_DATA_ARRAY 0xF3000000 |
| #define | MMU_ITLB_DATA_ARRAY2 0xF3800000 |
| #define | MMU_UTLB_ADDRESS_ARRAY 0xF6000000 |
| #define | MMU_UTLB_ADDRESS_ARRAY2 0xF6800000 |
| #define | MMU_UTLB_DATA_ARRAY 0xF7000000 |
| #define | MMU_UTLB_DATA_ARRAY2 0xF7800000 |
| #define | MMU_PAGE_ASSOC_BIT 0x80 |
| #define | MMUCR_AT (0) |
| #define | MMUCR_TI (1 << 2) |
| #define | MMUCR_URB 0x00FC0000 |
| #define | MMUCR_URB_SHIFT 18 |
| #define | MMUCR_URB_NENTRIES 64 |
| #define | MMUCR_URC 0x0000FC00 |
| #define | MMUCR_URC_SHIFT 10 |
| #define | MMUCR_SE (0) |
| #define | MMUCR_AEX (0) |
| #define | MMUCR_ME (0) |
| #define | MMUCR_SQMD (0) |
| #define | MMU_NTLB_ENTRIES 64 |
| #define | MMU_CONTROL_INIT |
| #define | TRA 0xff000020 |
| #define | EXPEVT 0xff000024 |
| #define | INTEVT 0xff000028 |
| #define EXPEVT 0xff000024 |
Definition at line 78 of file mmu_context.h.
| #define INTEVT 0xff000028 |
Definition at line 79 of file mmu_context.h.
| #define MMU_CONTROL_INIT |
Definition at line 74 of file mmu_context.h.
| #define MMU_ITLB_ADDRESS_ARRAY 0xF2000000 |
Definition at line 24 of file mmu_context.h.
| #define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000 |
Definition at line 25 of file mmu_context.h.
| #define MMU_ITLB_DATA_ARRAY 0xF3000000 |
Definition at line 26 of file mmu_context.h.
| #define MMU_ITLB_DATA_ARRAY2 0xF3800000 |
Definition at line 27 of file mmu_context.h.
| #define MMU_NTLB_ENTRIES 64 |
Definition at line 73 of file mmu_context.h.
| #define MMU_PAGE_ASSOC_BIT 0x80 |
Definition at line 33 of file mmu_context.h.
| #define MMU_PTEA 0xFF000034 /* PTE assistance register */ |
Definition at line 17 of file mmu_context.h.
| #define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */ |
Definition at line 18 of file mmu_context.h.
| #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */ |
Definition at line 13 of file mmu_context.h.
| #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */ |
Definition at line 14 of file mmu_context.h.
| #define MMU_TEA 0xFF00000C /* TLB Exception Address */ |
Definition at line 16 of file mmu_context.h.
| #define MMU_TLB_ENTRY_SHIFT 8 |
Definition at line 22 of file mmu_context.h.
| #define MMU_TTB 0xFF000008 /* Translation table base register */ |
Definition at line 15 of file mmu_context.h.
| #define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 |
Definition at line 29 of file mmu_context.h.
| #define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000 |
Definition at line 30 of file mmu_context.h.
| #define MMU_UTLB_DATA_ARRAY 0xF7000000 |
Definition at line 31 of file mmu_context.h.
| #define MMU_UTLB_DATA_ARRAY2 0xF7800000 |
Definition at line 32 of file mmu_context.h.
| #define MMUCR 0xFF000010 /* MMU Control Register */ |
Definition at line 20 of file mmu_context.h.
| #define MMUCR_AEX (0) |
Definition at line 58 of file mmu_context.h.
| #define MMUCR_AT (0) |
Definition at line 38 of file mmu_context.h.
| #define MMUCR_ME (0) |
Definition at line 64 of file mmu_context.h.
| #define MMUCR_SE (0) |
Definition at line 52 of file mmu_context.h.
| #define MMUCR_SQMD (0) |
Definition at line 70 of file mmu_context.h.
| #define MMUCR_TI (1 << 2) |
Definition at line 41 of file mmu_context.h.
| #define MMUCR_URB 0x00FC0000 |
Definition at line 43 of file mmu_context.h.
| #define MMUCR_URB_NENTRIES 64 |
Definition at line 45 of file mmu_context.h.
| #define MMUCR_URB_SHIFT 18 |
Definition at line 44 of file mmu_context.h.
| #define MMUCR_URC 0x0000FC00 |
Definition at line 46 of file mmu_context.h.
| #define MMUCR_URC_SHIFT 10 |
Definition at line 47 of file mmu_context.h.
| #define TRA 0xff000020 |
Definition at line 77 of file mmu_context.h.
1.8.2