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| #define CACHE_IC_ADDRESS_ARRAY 0x01000000 |
| #define CACHE_OC_ADDRESS_ARRAY 0x01800000 |
| #define CACHE_OC_N_SYNBITS 1 /* Number of synonym bits */ |
| #define CACHE_OC_SYN_MASK (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT) |
| #define CACHE_OC_SYN_SHIFT 12 |
| #define ICCR0_ICI 0x2 /* Invalidate all in IC */ |
| #define ICCR0_OFF 0x0 /* Set ICACHE off */ |
| #define ICCR0_ON 0x1 /* Set ICACHE on */ |
| #define ICCR1_NOLOCK 0x0 /* Set No Locking */ |
| #define ICCR_BASE 0x01600000 /* Instruction Cache Control Register */ |
| #define OCCR0_OCI 0x2 /* Invalidate all in OC */ |
| #define OCCR0_OFF 0x0 /* Set OCACHE off */ |
| #define OCCR0_ON 0x1 /* Set OCACHE on */ |
| #define OCCR0_WB 0x0 /* Set OCACHE in WB Mode */ |
| #define OCCR0_WT 0x4 /* Set OCACHE in WT Mode */ |
| #define OCCR1_NOLOCK 0x0 /* Set No Locking */ |
| #define OCCR_BASE 0x01E00000 /* Operand Cache Control Register */ |
| #define SH_CACHE_COMBINED 0 |
| #define SH_CACHE_MODE_WB (1LL<<1) |
| #define SH_CACHE_MODE_WT (1LL<<0) |
| #define SH_CACHE_UPDATED (1LL<<57) |
| #define SH_CACHE_VALID (1LL<<0) |
1.8.2