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perf_event.h File Reference

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Data Structures

union  cpuid10_eax
 
union  cpuid10_ebx
 
union  cpuid10_edx
 
struct  x86_pmu_capability
 

Macros

#define INTEL_PMC_MAX_GENERIC   32
 
#define INTEL_PMC_MAX_FIXED   3
 
#define INTEL_PMC_IDX_FIXED   32
 
#define X86_PMC_IDX_MAX   64
 
#define MSR_ARCH_PERFMON_PERFCTR0   0xc1
 
#define MSR_ARCH_PERFMON_PERFCTR1   0xc2
 
#define MSR_ARCH_PERFMON_EVENTSEL0   0x186
 
#define MSR_ARCH_PERFMON_EVENTSEL1   0x187
 
#define ARCH_PERFMON_EVENTSEL_EVENT   0x000000FFULL
 
#define ARCH_PERFMON_EVENTSEL_UMASK   0x0000FF00ULL
 
#define ARCH_PERFMON_EVENTSEL_USR   (1ULL << 16)
 
#define ARCH_PERFMON_EVENTSEL_OS   (1ULL << 17)
 
#define ARCH_PERFMON_EVENTSEL_EDGE   (1ULL << 18)
 
#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL   (1ULL << 19)
 
#define ARCH_PERFMON_EVENTSEL_INT   (1ULL << 20)
 
#define ARCH_PERFMON_EVENTSEL_ANY   (1ULL << 21)
 
#define ARCH_PERFMON_EVENTSEL_ENABLE   (1ULL << 22)
 
#define ARCH_PERFMON_EVENTSEL_INV   (1ULL << 23)
 
#define ARCH_PERFMON_EVENTSEL_CMASK   0xFF000000ULL
 
#define AMD_PERFMON_EVENTSEL_GUESTONLY   (1ULL << 40)
 
#define AMD_PERFMON_EVENTSEL_HOSTONLY   (1ULL << 41)
 
#define AMD64_EVENTSEL_EVENT   (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
 
#define INTEL_ARCH_EVENT_MASK   (ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
 
#define X86_RAW_EVENT_MASK
 
#define AMD64_RAW_EVENT_MASK
 
#define AMD64_NUM_COUNTERS   4
 
#define AMD64_NUM_COUNTERS_CORE   6
 
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL   0x3c
 
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK   (0x00 << 8)
 
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX   0
 
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT   (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
 
#define ARCH_PERFMON_BRANCH_MISSES_RETIRED   6
 
#define ARCH_PERFMON_EVENTS_COUNT   7
 
#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL   0x38d
 
#define MSR_ARCH_PERFMON_FIXED_CTR0   0x309
 
#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS   (INTEL_PMC_IDX_FIXED + 0)
 
#define MSR_ARCH_PERFMON_FIXED_CTR1   0x30a
 
#define INTEL_PMC_IDX_FIXED_CPU_CYCLES   (INTEL_PMC_IDX_FIXED + 1)
 
#define MSR_ARCH_PERFMON_FIXED_CTR2   0x30b
 
#define INTEL_PMC_IDX_FIXED_REF_CYCLES   (INTEL_PMC_IDX_FIXED + 2)
 
#define INTEL_PMC_MSK_FIXED_REF_CYCLES   (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
 
#define INTEL_PMC_IDX_FIXED_BTS   (INTEL_PMC_IDX_FIXED + 16)
 
#define IBS_CPUID_FEATURES   0x8000001b
 
#define IBS_CAPS_AVAIL   (1U<<0)
 
#define IBS_CAPS_FETCHSAM   (1U<<1)
 
#define IBS_CAPS_OPSAM   (1U<<2)
 
#define IBS_CAPS_RDWROPCNT   (1U<<3)
 
#define IBS_CAPS_OPCNT   (1U<<4)
 
#define IBS_CAPS_BRNTRGT   (1U<<5)
 
#define IBS_CAPS_OPCNTEXT   (1U<<6)
 
#define IBS_CAPS_RIPINVALIDCHK   (1U<<7)
 
#define IBS_CAPS_DEFAULT
 
#define IBSCTL   0x1cc
 
#define IBSCTL_LVT_OFFSET_VALID   (1ULL<<8)
 
#define IBSCTL_LVT_OFFSET_MASK   0x0F
 
#define IBS_FETCH_RAND_EN   (1ULL<<57)
 
#define IBS_FETCH_VAL   (1ULL<<49)
 
#define IBS_FETCH_ENABLE   (1ULL<<48)
 
#define IBS_FETCH_CNT   0xFFFF0000ULL
 
#define IBS_FETCH_MAX_CNT   0x0000FFFFULL
 
#define IBS_OP_CUR_CNT   (0xFFFF0ULL<<32)
 
#define IBS_OP_CNT_CTL   (1ULL<<19)
 
#define IBS_OP_VAL   (1ULL<<18)
 
#define IBS_OP_ENABLE   (1ULL<<17)
 
#define IBS_OP_MAX_CNT   0x0000FFFFULL
 
#define IBS_OP_MAX_CNT_EXT   0x007FFFFFULL /* not a register bit mask */
 
#define IBS_RIP_INVALID   (1ULL<<38)
 
#define arch_perf_out_copy_user   copy_from_user_nmi
 

Variables

union cpuid10_eax __attribute__
 

Macro Definition Documentation

#define AMD64_EVENTSEL_EVENT   (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))

Definition at line 35 of file perf_event.h.

#define AMD64_NUM_COUNTERS   4

Definition at line 49 of file perf_event.h.

#define AMD64_NUM_COUNTERS_CORE   6

Definition at line 50 of file perf_event.h.

#define AMD64_RAW_EVENT_MASK
Value:
AMD64_EVENTSEL_EVENT)

Definition at line 46 of file perf_event.h.

#define AMD_PERFMON_EVENTSEL_GUESTONLY   (1ULL << 40)

Definition at line 32 of file perf_event.h.

#define AMD_PERFMON_EVENTSEL_HOSTONLY   (1ULL << 41)

Definition at line 33 of file perf_event.h.

#define arch_perf_out_copy_user   copy_from_user_nmi

Definition at line 265 of file perf_event.h.

#define ARCH_PERFMON_BRANCH_MISSES_RETIRED   6

Definition at line 58 of file perf_event.h.

#define ARCH_PERFMON_EVENTS_COUNT   7

Definition at line 59 of file perf_event.h.

#define ARCH_PERFMON_EVENTSEL_ANY   (1ULL << 21)

Definition at line 27 of file perf_event.h.

#define ARCH_PERFMON_EVENTSEL_CMASK   0xFF000000ULL

Definition at line 30 of file perf_event.h.

#define ARCH_PERFMON_EVENTSEL_EDGE   (1ULL << 18)

Definition at line 24 of file perf_event.h.

#define ARCH_PERFMON_EVENTSEL_ENABLE   (1ULL << 22)

Definition at line 28 of file perf_event.h.

#define ARCH_PERFMON_EVENTSEL_EVENT   0x000000FFULL

Definition at line 20 of file perf_event.h.

#define ARCH_PERFMON_EVENTSEL_INT   (1ULL << 20)

Definition at line 26 of file perf_event.h.

#define ARCH_PERFMON_EVENTSEL_INV   (1ULL << 23)

Definition at line 29 of file perf_event.h.

#define ARCH_PERFMON_EVENTSEL_OS   (1ULL << 17)

Definition at line 23 of file perf_event.h.

#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL   (1ULL << 19)

Definition at line 25 of file perf_event.h.

#define ARCH_PERFMON_EVENTSEL_UMASK   0x0000FF00ULL

Definition at line 21 of file perf_event.h.

#define ARCH_PERFMON_EVENTSEL_USR   (1ULL << 16)

Definition at line 22 of file perf_event.h.

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX   0

Definition at line 54 of file perf_event.h.

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT   (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))

Definition at line 55 of file perf_event.h.

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL   0x3c

Definition at line 52 of file perf_event.h.

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK   (0x00 << 8)

Definition at line 53 of file perf_event.h.

#define IBS_CAPS_AVAIL   (1U<<0)

Definition at line 152 of file perf_event.h.

#define IBS_CAPS_BRNTRGT   (1U<<5)

Definition at line 157 of file perf_event.h.

#define IBS_CAPS_DEFAULT
Value:

Definition at line 161 of file perf_event.h.

#define IBS_CAPS_FETCHSAM   (1U<<1)

Definition at line 153 of file perf_event.h.

#define IBS_CAPS_OPCNT   (1U<<4)

Definition at line 156 of file perf_event.h.

#define IBS_CAPS_OPCNTEXT   (1U<<6)

Definition at line 158 of file perf_event.h.

#define IBS_CAPS_OPSAM   (1U<<2)

Definition at line 154 of file perf_event.h.

#define IBS_CAPS_RDWROPCNT   (1U<<3)

Definition at line 155 of file perf_event.h.

#define IBS_CAPS_RIPINVALIDCHK   (1U<<7)

Definition at line 159 of file perf_event.h.

#define IBS_CPUID_FEATURES   0x8000001b

Definition at line 146 of file perf_event.h.

#define IBS_FETCH_CNT   0xFFFF0000ULL

Definition at line 176 of file perf_event.h.

#define IBS_FETCH_ENABLE   (1ULL<<48)

Definition at line 175 of file perf_event.h.

#define IBS_FETCH_MAX_CNT   0x0000FFFFULL

Definition at line 177 of file perf_event.h.

#define IBS_FETCH_RAND_EN   (1ULL<<57)

Definition at line 173 of file perf_event.h.

#define IBS_FETCH_VAL   (1ULL<<49)

Definition at line 174 of file perf_event.h.

#define IBS_OP_CNT_CTL   (1ULL<<19)

Definition at line 182 of file perf_event.h.

#define IBS_OP_CUR_CNT   (0xFFFF0ULL<<32)

Definition at line 181 of file perf_event.h.

#define IBS_OP_ENABLE   (1ULL<<17)

Definition at line 184 of file perf_event.h.

#define IBS_OP_MAX_CNT   0x0000FFFFULL

Definition at line 185 of file perf_event.h.

#define IBS_OP_MAX_CNT_EXT   0x007FFFFFULL /* not a register bit mask */

Definition at line 186 of file perf_event.h.

#define IBS_OP_VAL   (1ULL<<18)

Definition at line 183 of file perf_event.h.

#define IBS_RIP_INVALID   (1ULL<<38)

Definition at line 187 of file perf_event.h.

#define IBSCTL   0x1cc

Definition at line 168 of file perf_event.h.

#define IBSCTL_LVT_OFFSET_MASK   0x0F

Definition at line 170 of file perf_event.h.

#define IBSCTL_LVT_OFFSET_VALID   (1ULL<<8)

Definition at line 169 of file perf_event.h.

#define INTEL_ARCH_EVENT_MASK   (ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)

Definition at line 37 of file perf_event.h.

#define INTEL_PMC_IDX_FIXED   32

Definition at line 10 of file perf_event.h.

#define INTEL_PMC_IDX_FIXED_BTS   (INTEL_PMC_IDX_FIXED + 16)

Definition at line 140 of file perf_event.h.

#define INTEL_PMC_IDX_FIXED_CPU_CYCLES   (INTEL_PMC_IDX_FIXED + 1)

Definition at line 126 of file perf_event.h.

#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS   (INTEL_PMC_IDX_FIXED + 0)

Definition at line 122 of file perf_event.h.

#define INTEL_PMC_IDX_FIXED_REF_CYCLES   (INTEL_PMC_IDX_FIXED + 2)

Definition at line 130 of file perf_event.h.

#define INTEL_PMC_MAX_FIXED   3

Definition at line 9 of file perf_event.h.

#define INTEL_PMC_MAX_GENERIC   32

Definition at line 8 of file perf_event.h.

#define INTEL_PMC_MSK_FIXED_REF_CYCLES   (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)

Definition at line 131 of file perf_event.h.

#define MSR_ARCH_PERFMON_EVENTSEL0   0x186

Definition at line 17 of file perf_event.h.

#define MSR_ARCH_PERFMON_EVENTSEL1   0x187

Definition at line 18 of file perf_event.h.

#define MSR_ARCH_PERFMON_FIXED_CTR0   0x309

Definition at line 121 of file perf_event.h.

#define MSR_ARCH_PERFMON_FIXED_CTR1   0x30a

Definition at line 125 of file perf_event.h.

#define MSR_ARCH_PERFMON_FIXED_CTR2   0x30b

Definition at line 129 of file perf_event.h.

#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL   0x38d

Definition at line 114 of file perf_event.h.

#define MSR_ARCH_PERFMON_PERFCTR0   0xc1

Definition at line 14 of file perf_event.h.

#define MSR_ARCH_PERFMON_PERFCTR1   0xc2

Definition at line 15 of file perf_event.h.

#define X86_PMC_IDX_MAX   64

Definition at line 12 of file perf_event.h.

#define X86_RAW_EVENT_MASK
Value:
ARCH_PERFMON_EVENTSEL_UMASK | \
ARCH_PERFMON_EVENTSEL_EDGE | \
ARCH_PERFMON_EVENTSEL_INV | \
ARCH_PERFMON_EVENTSEL_CMASK)

Definition at line 40 of file perf_event.h.

Variable Documentation