regs-ost.h File Reference

#include <mach/hardware.h>

Go to the source code of this file.

Macros
#define	OSMR0   io_p2v(0x40A00000) /* */
#define	OSMR1   io_p2v(0x40A00004) /* */
#define	OSMR2   io_p2v(0x40A00008) /* */
#define	OSMR3   io_p2v(0x40A0000C) /* */
#define	OSMR4   io_p2v(0x40A00080) /* */
#define	OSCR   io_p2v(0x40A00010) /* OS Timer Counter Register */
#define	OSCR4   io_p2v(0x40A00040) /* OS Timer Counter Register */
#define	OMCR4   io_p2v(0x40A000C0) /* */
#define	OSSR   io_p2v(0x40A00014) /* OS Timer Status Register */
#define	OWER   io_p2v(0x40A00018) /* OS Timer Watchdog Enable Register */
#define	OIER   io_p2v(0x40A0001C) /* OS Timer Interrupt Enable Register */
#define	OSSR_M3   (1 << 3) /* Match status channel 3 */
#define	OSSR_M2   (1 << 2) /* Match status channel 2 */
#define	OSSR_M1   (1 << 1) /* Match status channel 1 */
#define	OSSR_M0   (1 << 0) /* Match status channel 0 */
#define	OWER_WME   (1 << 0) /* Watchdog Match Enable */
#define	OIER_E3   (1 << 3) /* Interrupt enable channel 3 */
#define	OIER_E2   (1 << 2) /* Interrupt enable channel 2 */
#define	OIER_E1   (1 << 1) /* Interrupt enable channel 1 */
#define	OIER_E0   (1 << 0) /* Interrupt enable channel 0 */

Macro Definition Documentation

#define OIER   io_p2v(0x40A0001C) /* OS Timer Interrupt Enable Register */

Definition at line 20 of file regs-ost.h.

#define OIER_E0   (1 << 0) /* Interrupt enable channel 0 */

Definition at line 32 of file regs-ost.h.

#define OIER_E1   (1 << 1) /* Interrupt enable channel 1 */

Definition at line 31 of file regs-ost.h.

#define OIER_E2   (1 << 2) /* Interrupt enable channel 2 */

Definition at line 30 of file regs-ost.h.

#define OIER_E3   (1 << 3) /* Interrupt enable channel 3 */

Definition at line 29 of file regs-ost.h.

#define OMCR4   io_p2v(0x40A000C0) /* */

Definition at line 17 of file regs-ost.h.

#define OSCR   io_p2v(0x40A00010) /* OS Timer Counter Register */

Definition at line 15 of file regs-ost.h.

#define OSCR4   io_p2v(0x40A00040) /* OS Timer Counter Register */

Definition at line 16 of file regs-ost.h.

#define OSMR0   io_p2v(0x40A00000) /* */

Definition at line 10 of file regs-ost.h.

#define OSMR1   io_p2v(0x40A00004) /* */

Definition at line 11 of file regs-ost.h.

#define OSMR2   io_p2v(0x40A00008) /* */

Definition at line 12 of file regs-ost.h.

#define OSMR3   io_p2v(0x40A0000C) /* */

Definition at line 13 of file regs-ost.h.

#define OSMR4   io_p2v(0x40A00080) /* */

Definition at line 14 of file regs-ost.h.

#define OSSR   io_p2v(0x40A00014) /* OS Timer Status Register */

Definition at line 18 of file regs-ost.h.

#define OSSR_M0   (1 << 0) /* Match status channel 0 */

Definition at line 25 of file regs-ost.h.

#define OSSR_M1   (1 << 1) /* Match status channel 1 */

Definition at line 24 of file regs-ost.h.

#define OSSR_M2   (1 << 2) /* Match status channel 2 */

Definition at line 23 of file regs-ost.h.

#define OSSR_M3   (1 << 3) /* Match status channel 3 */

Definition at line 22 of file regs-ost.h.

#define OWER   io_p2v(0x40A00018) /* OS Timer Watchdog Enable Register */

Definition at line 19 of file regs-ost.h.

#define OWER_WME   (1 << 0) /* Watchdog Match Enable */

Definition at line 27 of file regs-ost.h.