#include <mach/gpio-nrs.h>

Macros
#define	S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)

#define	S3C2410_GPIO_LEAVE (0xFFFFFFFF)

#define	S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */

#define	S3C2410_GPIO_OUTPUT (0xFFFFFFF1)

#define	S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */

#define	S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */

#define	S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */

#define	S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)

#define	S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)

#define	S3C2410_GPACON S3C2410_GPIOREG(0x00)

#define	S3C2410_GPADAT S3C2410_GPIOREG(0x04)

#define	S3C2410_GPA0_ADDR0 (1<<0)

#define	S3C2410_GPA1_ADDR16 (1<<1)

#define	S3C2410_GPA2_ADDR17 (1<<2)

#define	S3C2410_GPA3_ADDR18 (1<<3)

#define	S3C2410_GPA4_ADDR19 (1<<4)

#define	S3C2410_GPA5_ADDR20 (1<<5)

#define	S3C2410_GPA6_ADDR21 (1<<6)

#define	S3C2410_GPA7_ADDR22 (1<<7)

#define	S3C2410_GPA8_ADDR23 (1<<8)

#define	S3C2410_GPA9_ADDR24 (1<<9)

#define	S3C2410_GPA10_ADDR25 (1<<10)

#define	S3C2410_GPA11_ADDR26 (1<<11)

#define	S3C2410_GPA12_nGCS1 (1<<12)

#define	S3C2410_GPA13_nGCS2 (1<<13)

#define	S3C2410_GPA14_nGCS3 (1<<14)

#define	S3C2410_GPA15_nGCS4 (1<<15)

#define	S3C2410_GPA16_nGCS5 (1<<16)

#define	S3C2410_GPA17_CLE (1<<17)

#define	S3C2410_GPA18_ALE (1<<18)

#define	S3C2410_GPA19_nFWE (1<<19)

#define	S3C2410_GPA20_nFRE (1<<20)

#define	S3C2410_GPA21_nRSTOUT (1<<21)

#define	S3C2410_GPA22_nFCE (1<<22)

#define	S3C2410_GPBCON S3C2410_GPIOREG(0x10)

#define	S3C2410_GPBDAT S3C2410_GPIOREG(0x14)

#define	S3C2410_GPBUP S3C2410_GPIOREG(0x18)

#define	S3C2410_GPB0_TOUT0 (0x02 << 0)

#define	S3C2410_GPB1_TOUT1 (0x02 << 2)

#define	S3C2410_GPB2_TOUT2 (0x02 << 4)

#define	S3C2410_GPB3_TOUT3 (0x02 << 6)

#define	S3C2410_GPB4_TCLK0 (0x02 << 8)

#define	S3C2410_GPB4_MASK (0x03 << 8)

#define	S3C2410_GPB5_nXBACK (0x02 << 10)

#define	S3C2443_GPB5_XBACK (0x03 << 10)

#define	S3C2410_GPB6_nXBREQ (0x02 << 12)

#define	S3C2443_GPB6_XBREQ (0x03 << 12)

#define	S3C2410_GPB7_nXDACK1 (0x02 << 14)

#define	S3C2443_GPB7_XDACK1 (0x03 << 14)

#define	S3C2410_GPB8_nXDREQ1 (0x02 << 16)

#define	S3C2410_GPB9_nXDACK0 (0x02 << 18)

#define	S3C2443_GPB9_XDACK0 (0x03 << 18)

#define	S3C2410_GPB10_nXDRE0 (0x02 << 20)

#define	S3C2443_GPB10_XDREQ0 (0x03 << 20)

#define	S3C2410_GPB_PUPDIS(x) (1<<(x))

#define	S3C2410_GPCCON S3C2410_GPIOREG(0x20)

#define	S3C2410_GPCDAT S3C2410_GPIOREG(0x24)

#define	S3C2410_GPCUP S3C2410_GPIOREG(0x28)

#define	S3C2410_GPC0_LEND (0x02 << 0)

#define	S3C2410_GPC1_VCLK (0x02 << 2)

#define	S3C2410_GPC2_VLINE (0x02 << 4)

#define	S3C2410_GPC3_VFRAME (0x02 << 6)

#define	S3C2410_GPC4_VM (0x02 << 8)

#define	S3C2410_GPC5_LCDVF0 (0x02 << 10)

#define	S3C2410_GPC6_LCDVF1 (0x02 << 12)

#define	S3C2410_GPC7_LCDVF2 (0x02 << 14)

#define	S3C2410_GPC8_VD0 (0x02 << 16)

#define	S3C2410_GPC9_VD1 (0x02 << 18)

#define	S3C2410_GPC10_VD2 (0x02 << 20)

#define	S3C2410_GPC11_VD3 (0x02 << 22)

#define	S3C2410_GPC12_VD4 (0x02 << 24)

#define	S3C2410_GPC13_VD5 (0x02 << 26)

#define	S3C2410_GPC14_VD6 (0x02 << 28)

#define	S3C2410_GPC15_VD7 (0x02 << 30)

#define	S3C2410_GPC_PUPDIS(x) (1<<(x))

#define	S3C2410_GPDCON S3C2410_GPIOREG(0x30)

#define	S3C2410_GPDDAT S3C2410_GPIOREG(0x34)

#define	S3C2410_GPDUP S3C2410_GPIOREG(0x38)

#define	S3C2410_GPD0_VD8 (0x02 << 0)

#define	S3C2442_GPD0_nSPICS1 (0x03 << 0)

#define	S3C2410_GPD1_VD9 (0x02 << 2)

#define	S3C2442_GPD1_SPICLK1 (0x03 << 2)

#define	S3C2410_GPD2_VD10 (0x02 << 4)

#define	S3C2410_GPD3_VD11 (0x02 << 6)

#define	S3C2410_GPD4_VD12 (0x02 << 8)

#define	S3C2410_GPD5_VD13 (0x02 << 10)

#define	S3C2410_GPD6_VD14 (0x02 << 12)

#define	S3C2410_GPD7_VD15 (0x02 << 14)

#define	S3C2410_GPD8_VD16 (0x02 << 16)

#define	S3C2440_GPD8_SPIMISO1 (0x03 << 16)

#define	S3C2410_GPD9_VD17 (0x02 << 18)

#define	S3C2440_GPD9_SPIMOSI1 (0x03 << 18)

#define	S3C2410_GPD10_VD18 (0x02 << 20)

#define	S3C2440_GPD10_SPICLK1 (0x03 << 20)

#define	S3C2410_GPD11_VD19 (0x02 << 22)

#define	S3C2410_GPD12_VD20 (0x02 << 24)

#define	S3C2410_GPD13_VD21 (0x02 << 26)

#define	S3C2410_GPD14_VD22 (0x02 << 28)

#define	S3C2410_GPD14_nSS1 (0x03 << 28)

#define	S3C2410_GPD15_VD23 (0x02 << 30)

#define	S3C2410_GPD15_nSS0 (0x03 << 30)

#define	S3C2410_GPD_PUPDIS(x) (1<<(x))

#define	S3C2410_GPECON S3C2410_GPIOREG(0x40)

#define	S3C2410_GPEDAT S3C2410_GPIOREG(0x44)

#define	S3C2410_GPEUP S3C2410_GPIOREG(0x48)

#define	S3C2410_GPE0_I2SLRCK (0x02 << 0)

#define	S3C2443_GPE0_AC_nRESET (0x03 << 0)

#define	S3C2410_GPE0_MASK (0x03 << 0)

#define	S3C2410_GPE1_I2SSCLK (0x02 << 2)

#define	S3C2443_GPE1_AC_SYNC (0x03 << 2)

#define	S3C2410_GPE1_MASK (0x03 << 2)

#define	S3C2410_GPE2_CDCLK (0x02 << 4)

#define	S3C2443_GPE2_AC_BITCLK (0x03 << 4)

#define	S3C2410_GPE3_I2SSDI (0x02 << 6)

#define	S3C2443_GPE3_AC_SDI (0x03 << 6)

#define	S3C2410_GPE3_nSS0 (0x03 << 6)

#define	S3C2410_GPE3_MASK (0x03 << 6)

#define	S3C2410_GPE4_I2SSDO (0x02 << 8)

#define	S3C2443_GPE4_AC_SDO (0x03 << 8)

#define	S3C2410_GPE4_I2SSDI (0x03 << 8)

#define	S3C2410_GPE4_MASK (0x03 << 8)

#define	S3C2410_GPE5_SDCLK (0x02 << 10)

#define	S3C2443_GPE5_SD1_CLK (0x02 << 10)

#define	S3C2443_GPE5_AC_BITCLK (0x03 << 10)

#define	S3C2410_GPE6_SDCMD (0x02 << 12)

#define	S3C2443_GPE6_SD1_CMD (0x02 << 12)

#define	S3C2443_GPE6_AC_SDI (0x03 << 12)

#define	S3C2410_GPE7_SDDAT0 (0x02 << 14)

#define	S3C2443_GPE5_SD1_DAT0 (0x02 << 14)

#define	S3C2443_GPE7_AC_SDO (0x03 << 14)

#define	S3C2410_GPE8_SDDAT1 (0x02 << 16)

#define	S3C2443_GPE8_SD1_DAT1 (0x02 << 16)

#define	S3C2443_GPE8_AC_SYNC (0x03 << 16)

#define	S3C2410_GPE9_SDDAT2 (0x02 << 18)

#define	S3C2443_GPE9_SD1_DAT2 (0x02 << 18)

#define	S3C2443_GPE9_AC_nRESET (0x03 << 18)

#define	S3C2410_GPE10_SDDAT3 (0x02 << 20)

#define	S3C2443_GPE10_SD1_DAT3 (0x02 << 20)

#define	S3C2410_GPE11_SPIMISO0 (0x02 << 22)

#define	S3C2410_GPE12_SPIMOSI0 (0x02 << 24)

#define	S3C2410_GPE13_SPICLK0 (0x02 << 26)

#define	S3C2410_GPE14_IICSCL (0x02 << 28)

#define	S3C2410_GPE14_MASK (0x03 << 28)

#define	S3C2410_GPE15_IICSDA (0x02 << 30)

#define	S3C2410_GPE15_MASK (0x03 << 30)

#define	S3C2440_GPE0_ACSYNC (0x03 << 0)

#define	S3C2440_GPE1_ACBITCLK (0x03 << 2)

#define	S3C2440_GPE2_ACRESET (0x03 << 4)

#define	S3C2440_GPE3_ACIN (0x03 << 6)

#define	S3C2440_GPE4_ACOUT (0x03 << 8)

#define	S3C2410_GPE_PUPDIS(x) (1<<(x))

#define	S3C2410_GPFCON S3C2410_GPIOREG(0x50)

#define	S3C2410_GPFDAT S3C2410_GPIOREG(0x54)

#define	S3C2410_GPFUP S3C2410_GPIOREG(0x58)

#define	S3C2410_GPF0_EINT0 (0x02 << 0)

#define	S3C2410_GPF1_EINT1 (0x02 << 2)

#define	S3C2410_GPF2_EINT2 (0x02 << 4)

#define	S3C2410_GPF3_EINT3 (0x02 << 6)

#define	S3C2410_GPF4_EINT4 (0x02 << 8)

#define	S3C2410_GPF5_EINT5 (0x02 << 10)

#define	S3C2410_GPF6_EINT6 (0x02 << 12)

#define	S3C2410_GPF7_EINT7 (0x02 << 14)

#define	S3C2410_GPF_PUPDIS(x) (1<<(x))

#define	S3C2410_GPGCON S3C2410_GPIOREG(0x60)

#define	S3C2410_GPGDAT S3C2410_GPIOREG(0x64)

#define	S3C2410_GPGUP S3C2410_GPIOREG(0x68)

#define	S3C2410_GPG0_EINT8 (0x02 << 0)

#define	S3C2410_GPG1_EINT9 (0x02 << 2)

#define	S3C2410_GPG2_EINT10 (0x02 << 4)

#define	S3C2410_GPG2_nSS0 (0x03 << 4)

#define	S3C2410_GPG3_EINT11 (0x02 << 6)

#define	S3C2410_GPG3_nSS1 (0x03 << 6)

#define	S3C2410_GPG4_EINT12 (0x02 << 8)

#define	S3C2410_GPG4_LCDPWREN (0x03 << 8)

#define	S3C2443_GPG4_LCDPWRDN (0x03 << 8)

#define	S3C2410_GPG5_EINT13 (0x02 << 10)

#define	S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */

#define	S3C2410_GPG6_EINT14 (0x02 << 12)

#define	S3C2410_GPG6_SPIMOSI1 (0x03 << 12)

#define	S3C2410_GPG7_EINT15 (0x02 << 14)

#define	S3C2410_GPG7_SPICLK1 (0x03 << 14)

#define	S3C2410_GPG8_EINT16 (0x02 << 16)

#define	S3C2410_GPG9_EINT17 (0x02 << 18)

#define	S3C2410_GPG10_EINT18 (0x02 << 20)

#define	S3C2410_GPG11_EINT19 (0x02 << 22)

#define	S3C2410_GPG11_TCLK1 (0x03 << 22)

#define	S3C2443_GPG11_CF_nIREQ (0x03 << 22)

#define	S3C2410_GPG12_EINT20 (0x02 << 24)

#define	S3C2410_GPG12_XMON (0x03 << 24)

#define	S3C2442_GPG12_nSPICS0 (0x03 << 24)

#define	S3C2443_GPG12_nINPACK (0x03 << 24)

#define	S3C2410_GPG13_EINT21 (0x02 << 26)

#define	S3C2410_GPG13_nXPON (0x03 << 26)

#define	S3C2443_GPG13_CF_nREG (0x03 << 26)

#define	S3C2410_GPG14_EINT22 (0x02 << 28)

#define	S3C2410_GPG14_YMON (0x03 << 28)

#define	S3C2443_GPG14_CF_RESET (0x03 << 28)

#define	S3C2410_GPG15_EINT23 (0x02 << 30)

#define	S3C2410_GPG15_nYPON (0x03 << 30)

#define	S3C2443_GPG15_CF_PWR (0x03 << 30)

#define	S3C2410_GPG_PUPDIS(x) (1<<(x))

#define	S3C2410_GPHCON S3C2410_GPIOREG(0x70)

#define	S3C2410_GPHDAT S3C2410_GPIOREG(0x74)

#define	S3C2410_GPHUP S3C2410_GPIOREG(0x78)

#define	S3C2410_GPH0_nCTS0 (0x02 << 0)

#define	S3C2416_GPH0_TXD0 (0x02 << 0)

#define	S3C2410_GPH1_nRTS0 (0x02 << 2)

#define	S3C2416_GPH1_RXD0 (0x02 << 2)

#define	S3C2410_GPH2_TXD0 (0x02 << 4)

#define	S3C2416_GPH2_TXD1 (0x02 << 4)

#define	S3C2410_GPH3_RXD0 (0x02 << 6)

#define	S3C2416_GPH3_RXD1 (0x02 << 6)

#define	S3C2410_GPH4_TXD1 (0x02 << 8)

#define	S3C2416_GPH4_TXD2 (0x02 << 8)

#define	S3C2410_GPH5_RXD1 (0x02 << 10)

#define	S3C2416_GPH5_RXD2 (0x02 << 10)

#define	S3C2410_GPH6_TXD2 (0x02 << 12)

#define	S3C2416_GPH6_TXD3 (0x02 << 12)

#define	S3C2410_GPH6_nRTS1 (0x03 << 12)

#define	S3C2416_GPH6_nRTS2 (0x03 << 12)

#define	S3C2410_GPH7_RXD2 (0x02 << 14)

#define	S3C2416_GPH7_RXD3 (0x02 << 14)

#define	S3C2410_GPH7_nCTS1 (0x03 << 14)

#define	S3C2416_GPH7_nCTS2 (0x03 << 14)

#define	S3C2410_GPH8_UCLK (0x02 << 16)

#define	S3C2416_GPH8_nCTS0 (0x02 << 16)

#define	S3C2410_GPH9_CLKOUT0 (0x02 << 18)

#define	S3C2442_GPH9_nSPICS0 (0x03 << 18)

#define	S3C2416_GPH9_nRTS0 (0x02 << 18)

#define	S3C2410_GPH10_CLKOUT1 (0x02 << 20)

#define	S3C2416_GPH10_nCTS1 (0x02 << 20)

#define	S3C2416_GPH11_nRTS1 (0x02 << 22)

#define	S3C2416_GPH12_EXTUARTCLK (0x02 << 24)

#define	S3C2416_GPH13_CLKOUT0 (0x02 << 26)

#define	S3C2416_GPH14_CLKOUT1 (0x02 << 28)

#define	S3C2413_GPJCON S3C2410_GPIOREG(0x80)

#define	S3C2413_GPJDAT S3C2410_GPIOREG(0x84)

#define	S3C2413_GPJUP S3C2410_GPIOREG(0x88)

#define	S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C)

#define	S3C2440_GPJCON S3C2410_GPIOREG(0xD0)

#define	S3C2440_GPJDAT S3C2410_GPIOREG(0xD4)

#define	S3C2440_GPJUP S3C2410_GPIOREG(0xD8)

#define	S3C2443_GPKCON S3C2410_GPIOREG(0xE0)

#define	S3C2443_GPKDAT S3C2410_GPIOREG(0xE4)

#define	S3C2443_GPKUP S3C2410_GPIOREG(0xE8)

#define	S3C2443_GPLCON S3C2410_GPIOREG(0xF0)

#define	S3C2443_GPLDAT S3C2410_GPIOREG(0xF4)

#define	S3C2443_GPLUP S3C2410_GPIOREG(0xF8)

#define	S3C2443_GPMCON S3C2410_GPIOREG(0x100)

#define	S3C2443_GPMDAT S3C2410_GPIOREG(0x104)

#define	S3C2443_GPMUP S3C2410_GPIOREG(0x108)

#define	S3C2410_MISCCR S3C2410_GPIOREG(0x80)

#define	S3C2410_DCLKCON S3C2410_GPIOREG(0x84)

#define	S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84)

#define	S3C2410_MISCCR_SPUCR_HEN (0<<0)

#define	S3C2410_MISCCR_SPUCR_HDIS (1<<0)

#define	S3C2410_MISCCR_SPUCR_LEN (0<<1)

#define	S3C2410_MISCCR_SPUCR_LDIS (1<<1)

#define	S3C2410_MISCCR_USBDEV (0<<3)

#define	S3C2410_MISCCR_USBHOST (1<<3)

#define	S3C2410_MISCCR_CLK0_MPLL (0<<4)

#define	S3C2410_MISCCR_CLK0_UPLL (1<<4)

#define	S3C2410_MISCCR_CLK0_FCLK (2<<4)

#define	S3C2410_MISCCR_CLK0_HCLK (3<<4)

#define	S3C2410_MISCCR_CLK0_PCLK (4<<4)

#define	S3C2410_MISCCR_CLK0_DCLK0 (5<<4)

#define	S3C2410_MISCCR_CLK0_MASK (7<<4)

#define	S3C2412_MISCCR_CLK0_RTC (2<<4)

#define	S3C2410_MISCCR_CLK1_MPLL (0<<8)

#define	S3C2410_MISCCR_CLK1_UPLL (1<<8)

#define	S3C2410_MISCCR_CLK1_FCLK (2<<8)

#define	S3C2410_MISCCR_CLK1_HCLK (3<<8)

#define	S3C2410_MISCCR_CLK1_PCLK (4<<8)

#define	S3C2410_MISCCR_CLK1_DCLK1 (5<<8)

#define	S3C2410_MISCCR_CLK1_MASK (7<<8)

#define	S3C2412_MISCCR_CLK1_CLKsrc (0<<8)

#define	S3C2410_MISCCR_USBSUSPND0 (1<<12)

#define	S3C2416_MISCCR_SEL_SUSPND (1<<12)

#define	S3C2410_MISCCR_USBSUSPND1 (1<<13)

#define	S3C2410_MISCCR_nRSTCON (1<<16)

#define	S3C2410_MISCCR_nEN_SCLK0 (1<<17)

#define	S3C2410_MISCCR_nEN_SCLK1 (1<<18)

#define	S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */

#define	S3C2410_MISCCR_SDSLEEP (7<<17)

#define	S3C2416_MISCCR_FLT_I2C (1<<24)

#define	S3C2416_MISCCR_HSSPI_EN2 (1<<31)

#define	S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)

#define	S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)

#define	S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)

#define	S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88)

#define	S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)

#define	S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)

#define	S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)

#define	S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)

#define	S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)

#define	S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)

#define	S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94)

#define	S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98)

#define	S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C)

#define	S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0)

#define	S3C2410_EINTFLT_PCLK (0x00)

#define	S3C2410_EINTFLT_EXTCLK (1<<7)

#define	S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f)

#define	S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)

#define	S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0)

#define	S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4)

#define	S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)

#define	S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)

#define	S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC)

#define	S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0)

#define	S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4)

#define	S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8)

#define	S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC)

#define	S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC)

#define	S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0)

#define	S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4)

#define	S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8)

#define	S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC)

#define	S3C2410_GSTATUS0_nWAIT (1<<3)

#define	S3C2410_GSTATUS0_NCON (1<<2)

#define	S3C2410_GSTATUS0_RnB (1<<1)

#define	S3C2410_GSTATUS0_nBATTFLT (1<<0)

#define	S3C2410_GSTATUS1_IDMASK (0xffff0000)

#define	S3C2410_GSTATUS1_2410 (0x32410000)

#define	S3C2410_GSTATUS1_2412 (0x32412001)

#define	S3C2410_GSTATUS1_2416 (0x32416003)

#define	S3C2410_GSTATUS1_2440 (0x32440000)

#define	S3C2410_GSTATUS1_2442 (0x32440aaa)

#define	S3C2410_GSTATUS1_2450 (0x32450003)

#define	S3C2410_GSTATUS2_WTRESET (1<<2)

#define	S3C2410_GSTATUS2_OFFRESET (1<<1)

#define	S3C2410_GSTATUS2_PONRESET (1<<0)

#define	S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)

#define	S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C)

#define	S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C)

#define	S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C)

#define	S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C)

#define	S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C)

#define	S3C2412_GPIO_SLPCON_LOW ( 0x00 )

#define	S3C2412_GPIO_SLPCON_HIGH ( 0x01 )

#define	S3C2412_GPIO_SLPCON_IN ( 0x02 )

#define	S3C2412_GPIO_SLPCON_PULL ( 0x03 )

#define	S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2))

#define	S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2))

#define	S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2))

#define	S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2))

#define	S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */

#define	S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2))

#define	S3C2412_SLPCON_ALL_LOW (0x0)

#define	S3C2412_SLPCON_ALL_HIGH (0x11111111 \| 0x44444444)

#define	S3C2412_SLPCON_ALL_IN (0x22222222 \| 0x88888888)

#define	S3C2412_SLPCON_ALL_PULL (0x33333333)

Macro Definition Documentation

#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)

Definition at line 462 of file regs-gpio.h.

#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)

Definition at line 529 of file regs-gpio.h.

#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)

Definition at line 530 of file regs-gpio.h.

#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)

Definition at line 531 of file regs-gpio.h.

#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)

Definition at line 532 of file regs-gpio.h.

#define S3C2410_EINTFLT_EXTCLK (1<<7)

Definition at line 541 of file regs-gpio.h.

#define S3C2410_EINTFLT_PCLK (0x00)

Definition at line 540 of file regs-gpio.h.

#define S3C2410_EINTFLT_WIDTHMSK ( x ) ((x) & 0x3f)

Definition at line 542 of file regs-gpio.h.

#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)

Definition at line 520 of file regs-gpio.h.

#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)

Definition at line 521 of file regs-gpio.h.

#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)

Definition at line 522 of file regs-gpio.h.

#define S3C2410_GPA0_ADDR0 (1<<0)

Definition at line 46 of file regs-gpio.h.

#define S3C2410_GPA10_ADDR25 (1<<10)

Definition at line 56 of file regs-gpio.h.

#define S3C2410_GPA11_ADDR26 (1<<11)

Definition at line 57 of file regs-gpio.h.

#define S3C2410_GPA12_nGCS1 (1<<12)

Definition at line 58 of file regs-gpio.h.

#define S3C2410_GPA13_nGCS2 (1<<13)

Definition at line 59 of file regs-gpio.h.

#define S3C2410_GPA14_nGCS3 (1<<14)

Definition at line 60 of file regs-gpio.h.

#define S3C2410_GPA15_nGCS4 (1<<15)

Definition at line 61 of file regs-gpio.h.

#define S3C2410_GPA16_nGCS5 (1<<16)

Definition at line 62 of file regs-gpio.h.

#define S3C2410_GPA17_CLE (1<<17)

Definition at line 63 of file regs-gpio.h.

#define S3C2410_GPA18_ALE (1<<18)

Definition at line 64 of file regs-gpio.h.

#define S3C2410_GPA19_nFWE (1<<19)

Definition at line 65 of file regs-gpio.h.

#define S3C2410_GPA1_ADDR16 (1<<1)

Definition at line 47 of file regs-gpio.h.

#define S3C2410_GPA20_nFRE (1<<20)

Definition at line 66 of file regs-gpio.h.

#define S3C2410_GPA21_nRSTOUT (1<<21)

Definition at line 67 of file regs-gpio.h.

#define S3C2410_GPA22_nFCE (1<<22)

Definition at line 68 of file regs-gpio.h.

#define S3C2410_GPA2_ADDR17 (1<<2)

Definition at line 48 of file regs-gpio.h.

#define S3C2410_GPA3_ADDR18 (1<<3)

Definition at line 49 of file regs-gpio.h.

#define S3C2410_GPA4_ADDR19 (1<<4)

Definition at line 50 of file regs-gpio.h.

#define S3C2410_GPA5_ADDR20 (1<<5)

Definition at line 51 of file regs-gpio.h.

#define S3C2410_GPA6_ADDR21 (1<<6)

Definition at line 52 of file regs-gpio.h.

#define S3C2410_GPA7_ADDR22 (1<<7)

Definition at line 53 of file regs-gpio.h.

#define S3C2410_GPA8_ADDR23 (1<<8)

Definition at line 54 of file regs-gpio.h.

#define S3C2410_GPA9_ADDR24 (1<<9)

Definition at line 55 of file regs-gpio.h.

#define S3C2410_GPACON S3C2410_GPIOREG(0x00)

Definition at line 43 of file regs-gpio.h.

#define S3C2410_GPADAT S3C2410_GPIOREG(0x04)

Definition at line 44 of file regs-gpio.h.

#define S3C2410_GPB0_TOUT0 (0x02 << 0)

Definition at line 87 of file regs-gpio.h.

#define S3C2410_GPB10_nXDRE0 (0x02 << 20)

Definition at line 112 of file regs-gpio.h.

#define S3C2410_GPB1_TOUT1 (0x02 << 2)

Definition at line 89 of file regs-gpio.h.

#define S3C2410_GPB2_TOUT2 (0x02 << 4)

Definition at line 91 of file regs-gpio.h.

#define S3C2410_GPB3_TOUT3 (0x02 << 6)

Definition at line 93 of file regs-gpio.h.

#define S3C2410_GPB4_MASK (0x03 << 8)

Definition at line 96 of file regs-gpio.h.

#define S3C2410_GPB4_TCLK0 (0x02 << 8)

Definition at line 95 of file regs-gpio.h.

#define S3C2410_GPB5_nXBACK (0x02 << 10)

Definition at line 98 of file regs-gpio.h.

#define S3C2410_GPB6_nXBREQ (0x02 << 12)

Definition at line 101 of file regs-gpio.h.

#define S3C2410_GPB7_nXDACK1 (0x02 << 14)

Definition at line 104 of file regs-gpio.h.

#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)

Definition at line 107 of file regs-gpio.h.

#define S3C2410_GPB9_nXDACK0 (0x02 << 18)

Definition at line 109 of file regs-gpio.h.

#define S3C2410_GPB_PUPDIS ( x ) (1<<(x))

Definition at line 115 of file regs-gpio.h.

#define S3C2410_GPBCON S3C2410_GPIOREG(0x10)

Definition at line 81 of file regs-gpio.h.

#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14)

Definition at line 82 of file regs-gpio.h.

#define S3C2410_GPBUP S3C2410_GPIOREG(0x18)

Definition at line 83 of file regs-gpio.h.

#define S3C2410_GPC0_LEND (0x02 << 0)

Definition at line 126 of file regs-gpio.h.

#define S3C2410_GPC10_VD2 (0x02 << 20)

Definition at line 136 of file regs-gpio.h.

#define S3C2410_GPC11_VD3 (0x02 << 22)

Definition at line 137 of file regs-gpio.h.

#define S3C2410_GPC12_VD4 (0x02 << 24)

Definition at line 138 of file regs-gpio.h.

#define S3C2410_GPC13_VD5 (0x02 << 26)

Definition at line 139 of file regs-gpio.h.

#define S3C2410_GPC14_VD6 (0x02 << 28)

Definition at line 140 of file regs-gpio.h.

#define S3C2410_GPC15_VD7 (0x02 << 30)

Definition at line 141 of file regs-gpio.h.

#define S3C2410_GPC1_VCLK (0x02 << 2)

Definition at line 127 of file regs-gpio.h.

#define S3C2410_GPC2_VLINE (0x02 << 4)

Definition at line 128 of file regs-gpio.h.

#define S3C2410_GPC3_VFRAME (0x02 << 6)

Definition at line 129 of file regs-gpio.h.

#define S3C2410_GPC4_VM (0x02 << 8)

Definition at line 130 of file regs-gpio.h.

#define S3C2410_GPC5_LCDVF0 (0x02 << 10)

Definition at line 131 of file regs-gpio.h.

#define S3C2410_GPC6_LCDVF1 (0x02 << 12)

Definition at line 132 of file regs-gpio.h.

#define S3C2410_GPC7_LCDVF2 (0x02 << 14)

Definition at line 133 of file regs-gpio.h.

#define S3C2410_GPC8_VD0 (0x02 << 16)

Definition at line 134 of file regs-gpio.h.

#define S3C2410_GPC9_VD1 (0x02 << 18)

Definition at line 135 of file regs-gpio.h.

#define S3C2410_GPC_PUPDIS ( x ) (1<<(x))

Definition at line 142 of file regs-gpio.h.

#define S3C2410_GPCCON S3C2410_GPIOREG(0x20)

Definition at line 123 of file regs-gpio.h.

#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)

Definition at line 124 of file regs-gpio.h.

#define S3C2410_GPCUP S3C2410_GPIOREG(0x28)

Definition at line 125 of file regs-gpio.h.

#define S3C2410_GPD0_VD8 (0x02 << 0)

Definition at line 157 of file regs-gpio.h.

#define S3C2410_GPD10_VD18 (0x02 << 20)

Definition at line 181 of file regs-gpio.h.

#define S3C2410_GPD11_VD19 (0x02 << 22)

Definition at line 184 of file regs-gpio.h.

#define S3C2410_GPD12_VD20 (0x02 << 24)

Definition at line 186 of file regs-gpio.h.

#define S3C2410_GPD13_VD21 (0x02 << 26)

Definition at line 188 of file regs-gpio.h.

#define S3C2410_GPD14_nSS1 (0x03 << 28)

Definition at line 191 of file regs-gpio.h.

#define S3C2410_GPD14_VD22 (0x02 << 28)

Definition at line 190 of file regs-gpio.h.

#define S3C2410_GPD15_nSS0 (0x03 << 30)

Definition at line 194 of file regs-gpio.h.

#define S3C2410_GPD15_VD23 (0x02 << 30)

Definition at line 193 of file regs-gpio.h.

#define S3C2410_GPD1_VD9 (0x02 << 2)

Definition at line 160 of file regs-gpio.h.

#define S3C2410_GPD2_VD10 (0x02 << 4)

Definition at line 163 of file regs-gpio.h.

#define S3C2410_GPD3_VD11 (0x02 << 6)

Definition at line 165 of file regs-gpio.h.

#define S3C2410_GPD4_VD12 (0x02 << 8)

Definition at line 167 of file regs-gpio.h.

#define S3C2410_GPD5_VD13 (0x02 << 10)

Definition at line 169 of file regs-gpio.h.

#define S3C2410_GPD6_VD14 (0x02 << 12)

Definition at line 171 of file regs-gpio.h.

#define S3C2410_GPD7_VD15 (0x02 << 14)

Definition at line 173 of file regs-gpio.h.

#define S3C2410_GPD8_VD16 (0x02 << 16)

Definition at line 175 of file regs-gpio.h.

#define S3C2410_GPD9_VD17 (0x02 << 18)

Definition at line 178 of file regs-gpio.h.

#define S3C2410_GPD_PUPDIS ( x ) (1<<(x))

Definition at line 196 of file regs-gpio.h.

#define S3C2410_GPDCON S3C2410_GPIOREG(0x30)

Definition at line 153 of file regs-gpio.h.

#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34)

Definition at line 154 of file regs-gpio.h.

#define S3C2410_GPDUP S3C2410_GPIOREG(0x38)

Definition at line 155 of file regs-gpio.h.

#define S3C2410_GPE0_I2SLRCK (0x02 << 0)

Definition at line 211 of file regs-gpio.h.

#define S3C2410_GPE0_MASK (0x03 << 0)

Definition at line 213 of file regs-gpio.h.

#define S3C2410_GPE10_SDDAT3 (0x02 << 20)

Definition at line 252 of file regs-gpio.h.

#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)

Definition at line 255 of file regs-gpio.h.

#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)

Definition at line 257 of file regs-gpio.h.

#define S3C2410_GPE13_SPICLK0 (0x02 << 26)

Definition at line 259 of file regs-gpio.h.

#define S3C2410_GPE14_IICSCL (0x02 << 28)

Definition at line 261 of file regs-gpio.h.

#define S3C2410_GPE14_MASK (0x03 << 28)

Definition at line 262 of file regs-gpio.h.

#define S3C2410_GPE15_IICSDA (0x02 << 30)

Definition at line 264 of file regs-gpio.h.

#define S3C2410_GPE15_MASK (0x03 << 30)

Definition at line 265 of file regs-gpio.h.

#define S3C2410_GPE1_I2SSCLK (0x02 << 2)

Definition at line 215 of file regs-gpio.h.

#define S3C2410_GPE1_MASK (0x03 << 2)

Definition at line 217 of file regs-gpio.h.

#define S3C2410_GPE2_CDCLK (0x02 << 4)

Definition at line 219 of file regs-gpio.h.

#define S3C2410_GPE3_I2SSDI (0x02 << 6)

Definition at line 222 of file regs-gpio.h.

#define S3C2410_GPE3_MASK (0x03 << 6)

Definition at line 225 of file regs-gpio.h.

#define S3C2410_GPE3_nSS0 (0x03 << 6)

Definition at line 224 of file regs-gpio.h.

#define S3C2410_GPE4_I2SSDI (0x03 << 8)

Definition at line 229 of file regs-gpio.h.

#define S3C2410_GPE4_I2SSDO (0x02 << 8)

Definition at line 227 of file regs-gpio.h.

#define S3C2410_GPE4_MASK (0x03 << 8)

Definition at line 230 of file regs-gpio.h.

#define S3C2410_GPE5_SDCLK (0x02 << 10)

Definition at line 232 of file regs-gpio.h.

#define S3C2410_GPE6_SDCMD (0x02 << 12)

Definition at line 236 of file regs-gpio.h.

#define S3C2410_GPE7_SDDAT0 (0x02 << 14)

Definition at line 240 of file regs-gpio.h.

#define S3C2410_GPE8_SDDAT1 (0x02 << 16)

Definition at line 244 of file regs-gpio.h.

#define S3C2410_GPE9_SDDAT2 (0x02 << 18)

Definition at line 248 of file regs-gpio.h.

#define S3C2410_GPE_PUPDIS ( x ) (1<<(x))

Definition at line 273 of file regs-gpio.h.

#define S3C2410_GPECON S3C2410_GPIOREG(0x40)

Definition at line 207 of file regs-gpio.h.

#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44)

Definition at line 208 of file regs-gpio.h.

#define S3C2410_GPEUP S3C2410_GPIOREG(0x48)

Definition at line 209 of file regs-gpio.h.

#define S3C2410_GPF0_EINT0 (0x02 << 0)

Definition at line 292 of file regs-gpio.h.

#define S3C2410_GPF1_EINT1 (0x02 << 2)

Definition at line 293 of file regs-gpio.h.

#define S3C2410_GPF2_EINT2 (0x02 << 4)

Definition at line 294 of file regs-gpio.h.

#define S3C2410_GPF3_EINT3 (0x02 << 6)

Definition at line 295 of file regs-gpio.h.

#define S3C2410_GPF4_EINT4 (0x02 << 8)

Definition at line 296 of file regs-gpio.h.

#define S3C2410_GPF5_EINT5 (0x02 << 10)

Definition at line 297 of file regs-gpio.h.

#define S3C2410_GPF6_EINT6 (0x02 << 12)

Definition at line 298 of file regs-gpio.h.

#define S3C2410_GPF7_EINT7 (0x02 << 14)

Definition at line 299 of file regs-gpio.h.

#define S3C2410_GPF_PUPDIS ( x ) (1<<(x))

Definition at line 300 of file regs-gpio.h.

#define S3C2410_GPFCON S3C2410_GPIOREG(0x50)

Definition at line 288 of file regs-gpio.h.

#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54)

Definition at line 289 of file regs-gpio.h.

#define S3C2410_GPFUP S3C2410_GPIOREG(0x58)

Definition at line 290 of file regs-gpio.h.

#define S3C2410_GPG0_EINT8 (0x02 << 0)

Definition at line 315 of file regs-gpio.h.

#define S3C2410_GPG10_EINT18 (0x02 << 20)

Definition at line 342 of file regs-gpio.h.

#define S3C2410_GPG11_EINT19 (0x02 << 22)

Definition at line 344 of file regs-gpio.h.

#define S3C2410_GPG11_TCLK1 (0x03 << 22)

Definition at line 345 of file regs-gpio.h.

#define S3C2410_GPG12_EINT20 (0x02 << 24)

Definition at line 348 of file regs-gpio.h.

#define S3C2410_GPG12_XMON (0x03 << 24)

Definition at line 349 of file regs-gpio.h.

#define S3C2410_GPG13_EINT21 (0x02 << 26)

Definition at line 353 of file regs-gpio.h.

#define S3C2410_GPG13_nXPON (0x03 << 26)

Definition at line 354 of file regs-gpio.h.

#define S3C2410_GPG14_EINT22 (0x02 << 28)

Definition at line 357 of file regs-gpio.h.

#define S3C2410_GPG14_YMON (0x03 << 28)

Definition at line 358 of file regs-gpio.h.

#define S3C2410_GPG15_EINT23 (0x02 << 30)

Definition at line 361 of file regs-gpio.h.

#define S3C2410_GPG15_nYPON (0x03 << 30)

Definition at line 362 of file regs-gpio.h.

#define S3C2410_GPG1_EINT9 (0x02 << 2)

Definition at line 317 of file regs-gpio.h.

#define S3C2410_GPG2_EINT10 (0x02 << 4)

Definition at line 319 of file regs-gpio.h.

#define S3C2410_GPG2_nSS0 (0x03 << 4)

Definition at line 320 of file regs-gpio.h.

#define S3C2410_GPG3_EINT11 (0x02 << 6)

Definition at line 322 of file regs-gpio.h.

#define S3C2410_GPG3_nSS1 (0x03 << 6)

Definition at line 323 of file regs-gpio.h.

#define S3C2410_GPG4_EINT12 (0x02 << 8)

Definition at line 325 of file regs-gpio.h.

#define S3C2410_GPG4_LCDPWREN (0x03 << 8)

Definition at line 326 of file regs-gpio.h.

#define S3C2410_GPG5_EINT13 (0x02 << 10)

Definition at line 329 of file regs-gpio.h.

#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */

Definition at line 330 of file regs-gpio.h.

#define S3C2410_GPG6_EINT14 (0x02 << 12)

Definition at line 332 of file regs-gpio.h.

#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)

Definition at line 333 of file regs-gpio.h.

#define S3C2410_GPG7_EINT15 (0x02 << 14)

Definition at line 335 of file regs-gpio.h.

#define S3C2410_GPG7_SPICLK1 (0x03 << 14)

Definition at line 336 of file regs-gpio.h.

#define S3C2410_GPG8_EINT16 (0x02 << 16)

Definition at line 338 of file regs-gpio.h.

#define S3C2410_GPG9_EINT17 (0x02 << 18)

Definition at line 340 of file regs-gpio.h.

#define S3C2410_GPG_PUPDIS ( x ) (1<<(x))

Definition at line 365 of file regs-gpio.h.

#define S3C2410_GPGCON S3C2410_GPIOREG(0x60)

Definition at line 311 of file regs-gpio.h.

#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)

Definition at line 312 of file regs-gpio.h.

#define S3C2410_GPGUP S3C2410_GPIOREG(0x68)

Definition at line 313 of file regs-gpio.h.

#define S3C2410_GPH0_nCTS0 (0x02 << 0)

Definition at line 379 of file regs-gpio.h.

#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)

Definition at line 414 of file regs-gpio.h.

#define S3C2410_GPH1_nRTS0 (0x02 << 2)

Definition at line 382 of file regs-gpio.h.

#define S3C2410_GPH2_TXD0 (0x02 << 4)

Definition at line 385 of file regs-gpio.h.

#define S3C2410_GPH3_RXD0 (0x02 << 6)

Definition at line 388 of file regs-gpio.h.

#define S3C2410_GPH4_TXD1 (0x02 << 8)

Definition at line 391 of file regs-gpio.h.

#define S3C2410_GPH5_RXD1 (0x02 << 10)

Definition at line 394 of file regs-gpio.h.

#define S3C2410_GPH6_nRTS1 (0x03 << 12)

Definition at line 399 of file regs-gpio.h.

#define S3C2410_GPH6_TXD2 (0x02 << 12)

Definition at line 397 of file regs-gpio.h.

#define S3C2410_GPH7_nCTS1 (0x03 << 14)

Definition at line 404 of file regs-gpio.h.

#define S3C2410_GPH7_RXD2 (0x02 << 14)

Definition at line 402 of file regs-gpio.h.

#define S3C2410_GPH8_UCLK (0x02 << 16)

Definition at line 407 of file regs-gpio.h.

#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)

Definition at line 410 of file regs-gpio.h.

#define S3C2410_GPHCON S3C2410_GPIOREG(0x70)

Definition at line 375 of file regs-gpio.h.

#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)

Definition at line 376 of file regs-gpio.h.

#define S3C2410_GPHUP S3C2410_GPIOREG(0x78)

Definition at line 377 of file regs-gpio.h.

#define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */

Definition at line 24 of file regs-gpio.h.

#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */

Definition at line 26 of file regs-gpio.h.

#define S3C2410_GPIO_LEAVE (0xFFFFFFFF)

Definition at line 23 of file regs-gpio.h.

#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1)

Definition at line 25 of file regs-gpio.h.

#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */

Definition at line 27 of file regs-gpio.h.

#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */

Definition at line 28 of file regs-gpio.h.

#define S3C2410_GPIOREG ( x ) ((x) + S3C24XX_VA_GPIO)

Definition at line 34 of file regs-gpio.h.

#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)

Definition at line 551 of file regs-gpio.h.

#define S3C2410_GSTATUS0_nBATTFLT (1<<0)

Definition at line 572 of file regs-gpio.h.

#define S3C2410_GSTATUS0_NCON (1<<2)

Definition at line 570 of file regs-gpio.h.

#define S3C2410_GSTATUS0_nWAIT (1<<3)

Definition at line 569 of file regs-gpio.h.

#define S3C2410_GSTATUS0_RnB (1<<1)

Definition at line 571 of file regs-gpio.h.

#define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0)

Definition at line 552 of file regs-gpio.h.

#define S3C2410_GSTATUS1_2410 (0x32410000)

Definition at line 575 of file regs-gpio.h.

#define S3C2410_GSTATUS1_2412 (0x32412001)

Definition at line 576 of file regs-gpio.h.

#define S3C2410_GSTATUS1_2416 (0x32416003)

Definition at line 577 of file regs-gpio.h.

#define S3C2410_GSTATUS1_2440 (0x32440000)

Definition at line 578 of file regs-gpio.h.

#define S3C2410_GSTATUS1_2442 (0x32440aaa)

Definition at line 579 of file regs-gpio.h.

#define S3C2410_GSTATUS1_2450 (0x32450003)

Definition at line 581 of file regs-gpio.h.

#define S3C2410_GSTATUS1_IDMASK (0xffff0000)

Definition at line 574 of file regs-gpio.h.

#define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4)

Definition at line 553 of file regs-gpio.h.

#define S3C2410_GSTATUS2_OFFRESET (1<<1)

Definition at line 584 of file regs-gpio.h.

#define S3C2410_GSTATUS2_PONRESET (1<<0)

Definition at line 585 of file regs-gpio.h.

#define S3C2410_GSTATUS2_WTRESET (1<<2)

Definition at line 583 of file regs-gpio.h.

#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)

Definition at line 554 of file regs-gpio.h.

#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)

Definition at line 555 of file regs-gpio.h.

#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)

Definition at line 461 of file regs-gpio.h.

#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)

Definition at line 482 of file regs-gpio.h.

#define S3C2410_MISCCR_CLK0_FCLK (2<<4)

Definition at line 479 of file regs-gpio.h.

#define S3C2410_MISCCR_CLK0_HCLK (3<<4)

Definition at line 480 of file regs-gpio.h.

#define S3C2410_MISCCR_CLK0_MASK (7<<4)

Definition at line 483 of file regs-gpio.h.

#define S3C2410_MISCCR_CLK0_MPLL (0<<4)

Definition at line 477 of file regs-gpio.h.

#define S3C2410_MISCCR_CLK0_PCLK (4<<4)

Definition at line 481 of file regs-gpio.h.

#define S3C2410_MISCCR_CLK0_UPLL (1<<4)

Definition at line 478 of file regs-gpio.h.

#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)

Definition at line 492 of file regs-gpio.h.

#define S3C2410_MISCCR_CLK1_FCLK (2<<8)

Definition at line 489 of file regs-gpio.h.

#define S3C2410_MISCCR_CLK1_HCLK (3<<8)

Definition at line 490 of file regs-gpio.h.

#define S3C2410_MISCCR_CLK1_MASK (7<<8)

Definition at line 493 of file regs-gpio.h.

#define S3C2410_MISCCR_CLK1_MPLL (0<<8)

Definition at line 487 of file regs-gpio.h.

#define S3C2410_MISCCR_CLK1_PCLK (4<<8)

Definition at line 491 of file regs-gpio.h.

#define S3C2410_MISCCR_CLK1_UPLL (1<<8)

Definition at line 488 of file regs-gpio.h.

#define S3C2410_MISCCR_nEN_SCLK0 (1<<17)

Definition at line 503 of file regs-gpio.h.

#define S3C2410_MISCCR_nEN_SCLK1 (1<<18)

Definition at line 504 of file regs-gpio.h.

#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */

Definition at line 505 of file regs-gpio.h.

#define S3C2410_MISCCR_nRSTCON (1<<16)

Definition at line 501 of file regs-gpio.h.

#define S3C2410_MISCCR_SDSLEEP (7<<17)

Definition at line 506 of file regs-gpio.h.

#define S3C2410_MISCCR_SPUCR_HDIS (1<<0)

Definition at line 470 of file regs-gpio.h.

#define S3C2410_MISCCR_SPUCR_HEN (0<<0)

Definition at line 469 of file regs-gpio.h.

#define S3C2410_MISCCR_SPUCR_LDIS (1<<1)

Definition at line 472 of file regs-gpio.h.

#define S3C2410_MISCCR_SPUCR_LEN (0<<1)

Definition at line 471 of file regs-gpio.h.

#define S3C2410_MISCCR_USBDEV (0<<3)

Definition at line 474 of file regs-gpio.h.

#define S3C2410_MISCCR_USBHOST (1<<3)

Definition at line 475 of file regs-gpio.h.

#define S3C2410_MISCCR_USBSUSPND0 (1<<12)

Definition at line 497 of file regs-gpio.h.

#define S3C2410_MISCCR_USBSUSPND1 (1<<13)

Definition at line 499 of file regs-gpio.h.

#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)

Definition at line 589 of file regs-gpio.h.

#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C)

Definition at line 590 of file regs-gpio.h.

#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C)

Definition at line 591 of file regs-gpio.h.

#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C)

Definition at line 592 of file regs-gpio.h.

#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C)

Definition at line 593 of file regs-gpio.h.

#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C)

Definition at line 594 of file regs-gpio.h.

#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 )

Definition at line 598 of file regs-gpio.h.

#define S3C2412_GPIO_SLPCON_IN ( 0x02 )

Definition at line 599 of file regs-gpio.h.

#define S3C2412_GPIO_SLPCON_LOW ( 0x00 )

Definition at line 597 of file regs-gpio.h.

#define S3C2412_GPIO_SLPCON_PULL ( 0x03 )

Definition at line 600 of file regs-gpio.h.

#define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC)

Definition at line 557 of file regs-gpio.h.

#define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0)

Definition at line 558 of file regs-gpio.h.

#define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4)

Definition at line 559 of file regs-gpio.h.

#define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8)

Definition at line 560 of file regs-gpio.h.

#define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC)

Definition at line 561 of file regs-gpio.h.

#define S3C2412_MISCCR_CLK0_RTC (2<<4)

Definition at line 485 of file regs-gpio.h.

#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8)

Definition at line 495 of file regs-gpio.h.

#define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444)

Definition at line 610 of file regs-gpio.h.

#define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888)

Definition at line 611 of file regs-gpio.h.

#define S3C2412_SLPCON_ALL_LOW (0x0)

Definition at line 609 of file regs-gpio.h.

#define S3C2412_SLPCON_ALL_PULL (0x33333333)

Definition at line 612 of file regs-gpio.h.

#define S3C2412_SLPCON_EINT ( x ) ( 0x02 << ((x) * 2)) /* only IRQ pins */

Definition at line 606 of file regs-gpio.h.

#define S3C2412_SLPCON_HIGH ( x ) ( 0x01 << ((x) * 2))

Definition at line 603 of file regs-gpio.h.

#define S3C2412_SLPCON_IN ( x ) ( 0x02 << ((x) * 2))

Definition at line 604 of file regs-gpio.h.

#define S3C2412_SLPCON_LOW ( x ) ( 0x00 << ((x) * 2))

Definition at line 602 of file regs-gpio.h.

#define S3C2412_SLPCON_MASK ( x ) ( 0x03 << ((x) * 2))

Definition at line 607 of file regs-gpio.h.

#define S3C2412_SLPCON_PULL ( x ) ( 0x03 << ((x) * 2))

Definition at line 605 of file regs-gpio.h.

#define S3C2413_GPJCON S3C2410_GPIOREG(0x80)

Definition at line 438 of file regs-gpio.h.

#define S3C2413_GPJDAT S3C2410_GPIOREG(0x84)

Definition at line 439 of file regs-gpio.h.

#define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C)

Definition at line 441 of file regs-gpio.h.

#define S3C2413_GPJUP S3C2410_GPIOREG(0x88)

Definition at line 440 of file regs-gpio.h.

#define S3C2416_GPH0_TXD0 (0x02 << 0)

Definition at line 380 of file regs-gpio.h.

#define S3C2416_GPH10_nCTS1 (0x02 << 20)

Definition at line 415 of file regs-gpio.h.

#define S3C2416_GPH11_nRTS1 (0x02 << 22)

Definition at line 417 of file regs-gpio.h.

#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24)

Definition at line 419 of file regs-gpio.h.

#define S3C2416_GPH13_CLKOUT0 (0x02 << 26)

Definition at line 421 of file regs-gpio.h.

#define S3C2416_GPH14_CLKOUT1 (0x02 << 28)

Definition at line 423 of file regs-gpio.h.

#define S3C2416_GPH1_RXD0 (0x02 << 2)

Definition at line 383 of file regs-gpio.h.

#define S3C2416_GPH2_TXD1 (0x02 << 4)

Definition at line 386 of file regs-gpio.h.

#define S3C2416_GPH3_RXD1 (0x02 << 6)

Definition at line 389 of file regs-gpio.h.

#define S3C2416_GPH4_TXD2 (0x02 << 8)

Definition at line 392 of file regs-gpio.h.

#define S3C2416_GPH5_RXD2 (0x02 << 10)

Definition at line 395 of file regs-gpio.h.

#define S3C2416_GPH6_nRTS2 (0x03 << 12)

Definition at line 400 of file regs-gpio.h.

#define S3C2416_GPH6_TXD3 (0x02 << 12)

Definition at line 398 of file regs-gpio.h.

#define S3C2416_GPH7_nCTS2 (0x03 << 14)

Definition at line 405 of file regs-gpio.h.

#define S3C2416_GPH7_RXD3 (0x02 << 14)

Definition at line 403 of file regs-gpio.h.

#define S3C2416_GPH8_nCTS0 (0x02 << 16)

Definition at line 408 of file regs-gpio.h.

#define S3C2416_GPH9_nRTS0 (0x02 << 18)

Definition at line 412 of file regs-gpio.h.

#define S3C2416_MISCCR_FLT_I2C (1<<24)

Definition at line 508 of file regs-gpio.h.

#define S3C2416_MISCCR_HSSPI_EN2 (1<<31)

Definition at line 509 of file regs-gpio.h.

#define S3C2416_MISCCR_SEL_SUSPND (1<<12)

Definition at line 498 of file regs-gpio.h.

#define S3C2440_GPD10_SPICLK1 (0x03 << 20)

Definition at line 182 of file regs-gpio.h.

#define S3C2440_GPD8_SPIMISO1 (0x03 << 16)

Definition at line 176 of file regs-gpio.h.

#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18)

Definition at line 179 of file regs-gpio.h.

#define S3C2440_GPE0_ACSYNC (0x03 << 0)

Definition at line 267 of file regs-gpio.h.

#define S3C2440_GPE1_ACBITCLK (0x03 << 2)

Definition at line 268 of file regs-gpio.h.

#define S3C2440_GPE2_ACRESET (0x03 << 4)

Definition at line 269 of file regs-gpio.h.

#define S3C2440_GPE3_ACIN (0x03 << 6)

Definition at line 270 of file regs-gpio.h.

#define S3C2440_GPE4_ACOUT (0x03 << 8)

Definition at line 271 of file regs-gpio.h.

#define S3C2440_GPJCON S3C2410_GPIOREG(0xD0)

Definition at line 444 of file regs-gpio.h.

#define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4)

Definition at line 445 of file regs-gpio.h.

#define S3C2440_GPJUP S3C2410_GPIOREG(0xD8)

Definition at line 446 of file regs-gpio.h.

#define S3C2442_GPD0_nSPICS1 (0x03 << 0)

Definition at line 158 of file regs-gpio.h.

#define S3C2442_GPD1_SPICLK1 (0x03 << 2)

Definition at line 161 of file regs-gpio.h.

#define S3C2442_GPG12_nSPICS0 (0x03 << 24)

Definition at line 350 of file regs-gpio.h.

#define S3C2442_GPH9_nSPICS0 (0x03 << 18)

Definition at line 411 of file regs-gpio.h.

#define S3C2443_GPB10_XDREQ0 (0x03 << 20)

Definition at line 113 of file regs-gpio.h.

#define S3C2443_GPB5_XBACK (0x03 << 10)

Definition at line 99 of file regs-gpio.h.

#define S3C2443_GPB6_XBREQ (0x03 << 12)

Definition at line 102 of file regs-gpio.h.

#define S3C2443_GPB7_XDACK1 (0x03 << 14)

Definition at line 105 of file regs-gpio.h.

#define S3C2443_GPB9_XDACK0 (0x03 << 18)

Definition at line 110 of file regs-gpio.h.

#define S3C2443_GPE0_AC_nRESET (0x03 << 0)

Definition at line 212 of file regs-gpio.h.

#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)

Definition at line 253 of file regs-gpio.h.

#define S3C2443_GPE1_AC_SYNC (0x03 << 2)

Definition at line 216 of file regs-gpio.h.

#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)

Definition at line 220 of file regs-gpio.h.

#define S3C2443_GPE3_AC_SDI (0x03 << 6)

Definition at line 223 of file regs-gpio.h.

#define S3C2443_GPE4_AC_SDO (0x03 << 8)

Definition at line 228 of file regs-gpio.h.

#define S3C2443_GPE5_AC_BITCLK (0x03 << 10)

Definition at line 234 of file regs-gpio.h.

#define S3C2443_GPE5_SD1_CLK (0x02 << 10)

Definition at line 233 of file regs-gpio.h.

#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)

Definition at line 241 of file regs-gpio.h.

#define S3C2443_GPE6_AC_SDI (0x03 << 12)

Definition at line 238 of file regs-gpio.h.

#define S3C2443_GPE6_SD1_CMD (0x02 << 12)

Definition at line 237 of file regs-gpio.h.

#define S3C2443_GPE7_AC_SDO (0x03 << 14)

Definition at line 242 of file regs-gpio.h.

#define S3C2443_GPE8_AC_SYNC (0x03 << 16)

Definition at line 246 of file regs-gpio.h.

#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)

Definition at line 245 of file regs-gpio.h.

#define S3C2443_GPE9_AC_nRESET (0x03 << 18)

Definition at line 250 of file regs-gpio.h.

#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)

Definition at line 249 of file regs-gpio.h.

#define S3C2443_GPG11_CF_nIREQ (0x03 << 22)

Definition at line 346 of file regs-gpio.h.

#define S3C2443_GPG12_nINPACK (0x03 << 24)

Definition at line 351 of file regs-gpio.h.

#define S3C2443_GPG13_CF_nREG (0x03 << 26)

Definition at line 355 of file regs-gpio.h.

#define S3C2443_GPG14_CF_RESET (0x03 << 28)

Definition at line 359 of file regs-gpio.h.

#define S3C2443_GPG15_CF_PWR (0x03 << 30)

Definition at line 363 of file regs-gpio.h.

#define S3C2443_GPG4_LCDPWRDN (0x03 << 8)

Definition at line 327 of file regs-gpio.h.

#define S3C2443_GPKCON S3C2410_GPIOREG(0xE0)

Definition at line 448 of file regs-gpio.h.

#define S3C2443_GPKDAT S3C2410_GPIOREG(0xE4)

Definition at line 449 of file regs-gpio.h.

#define S3C2443_GPKUP S3C2410_GPIOREG(0xE8)

Definition at line 450 of file regs-gpio.h.

#define S3C2443_GPLCON S3C2410_GPIOREG(0xF0)

Definition at line 452 of file regs-gpio.h.

#define S3C2443_GPLDAT S3C2410_GPIOREG(0xF4)

Definition at line 453 of file regs-gpio.h.

#define S3C2443_GPLUP S3C2410_GPIOREG(0xF8)

Definition at line 454 of file regs-gpio.h.

#define S3C2443_GPMCON S3C2410_GPIOREG(0x100)

Definition at line 456 of file regs-gpio.h.

#define S3C2443_GPMDAT S3C2410_GPIOREG(0x104)

Definition at line 457 of file regs-gpio.h.

#define S3C2443_GPMUP S3C2410_GPIOREG(0x108)

Definition at line 458 of file regs-gpio.h.

#define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84)

Definition at line 464 of file regs-gpio.h.

#define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94)

Definition at line 534 of file regs-gpio.h.

#define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98)

Definition at line 535 of file regs-gpio.h.

#define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C)

Definition at line 536 of file regs-gpio.h.

#define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0)

Definition at line 537 of file regs-gpio.h.

#define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88)

Definition at line 524 of file regs-gpio.h.

#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)

Definition at line 525 of file regs-gpio.h.

#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)

Definition at line 526 of file regs-gpio.h.

#define S3C24XX_GPIOREG2 ( x ) ((x) + S3C24XX_VA_GPIO2)

Definition at line 35 of file regs-gpio.h.

#define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC)

Definition at line 563 of file regs-gpio.h.

#define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0)

Definition at line 564 of file regs-gpio.h.

#define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4)

Definition at line 565 of file regs-gpio.h.

#define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8)

Definition at line 566 of file regs-gpio.h.

#define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC)

Definition at line 567 of file regs-gpio.h.

#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)

Definition at line 19 of file regs-gpio.h.

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