regs-spi.h File Reference

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Macros
#define	S3C2410_SPI1   (0x20)
#define	S3C2412_SPI1   (0x100)
#define	S3C2410_SPCON   (0x00)
#define	S3C2410_SPCON_SMOD_DMA   (2 << 5) /* DMA mode */
#define	S3C2410_SPCON_SMOD_INT   (1 << 5) /* interrupt mode */
#define	S3C2410_SPCON_SMOD_POLL   (0 << 5) /* polling mode */
#define	S3C2410_SPCON_ENSCK   (1 << 4) /* Enable SCK */
#define	S3C2410_SPCON_MSTR   (1 << 3) /* Master:1, Slave:0 select */
#define	S3C2410_SPCON_CPOL_HIGH   (1 << 2) /* Clock polarity select */
#define	S3C2410_SPCON_CPOL_LOW   (0 << 2) /* Clock polarity select */
#define	S3C2410_SPCON_CPHA_FMTB   (1 << 1) /* Clock Phase Select */
#define	S3C2410_SPCON_CPHA_FMTA   (0 << 1) /* Clock Phase Select */
#define	S3C2410_SPSTA   (0x04)
#define	S3C2410_SPSTA_DCOL   (1 << 2) /* Data Collision Error */
#define	S3C2410_SPSTA_MULD   (1 << 1) /* Multi Master Error */
#define	S3C2410_SPSTA_READY   (1 << 0) /* Data Tx/Rx ready */
#define	S3C2412_SPSTA_READY_ORG   (1 << 3)
#define	S3C2410_SPPIN   (0x08)
#define	S3C2410_SPPIN_ENMUL   (1 << 2) /* Multi Master Error detect */
#define	S3C2410_SPPIN_RESERVED   (1 << 1)
#define	S3C2410_SPPIN_KEEP   (1 << 0) /* Master Out keep */
#define	S3C2410_SPPRE   (0x0C)
#define	S3C2410_SPTDAT   (0x10)
#define	S3C2410_SPRDAT   (0x14)

Macro Definition Documentation

#define S3C2410_SPCON   (0x00)

Definition at line 18 of file regs-spi.h.

#define S3C2410_SPCON_CPHA_FMTA   (0 << 1) /* Clock Phase Select */

Definition at line 29 of file regs-spi.h.

#define S3C2410_SPCON_CPHA_FMTB   (1 << 1) /* Clock Phase Select */

Definition at line 28 of file regs-spi.h.

#define S3C2410_SPCON_CPOL_HIGH   (1 << 2) /* Clock polarity select */

Definition at line 25 of file regs-spi.h.

#define S3C2410_SPCON_CPOL_LOW   (0 << 2) /* Clock polarity select */

Definition at line 26 of file regs-spi.h.

#define S3C2410_SPCON_ENSCK   (1 << 4) /* Enable SCK */

Definition at line 23 of file regs-spi.h.

#define S3C2410_SPCON_MSTR   (1 << 3) /* Master:1, Slave:0 select */

Definition at line 24 of file regs-spi.h.

#define S3C2410_SPCON_SMOD_DMA   (2 << 5) /* DMA mode */

Definition at line 20 of file regs-spi.h.

#define S3C2410_SPCON_SMOD_INT   (1 << 5) /* interrupt mode */

Definition at line 21 of file regs-spi.h.

#define S3C2410_SPCON_SMOD_POLL   (0 << 5) /* polling mode */

Definition at line 22 of file regs-spi.h.

#define S3C2410_SPI1   (0x20)

Definition at line 15 of file regs-spi.h.

#define S3C2410_SPPIN   (0x08)

Definition at line 38 of file regs-spi.h.

#define S3C2410_SPPIN_ENMUL   (1 << 2) /* Multi Master Error detect */

Definition at line 40 of file regs-spi.h.

#define S3C2410_SPPIN_KEEP   (1 << 0) /* Master Out keep */

Definition at line 42 of file regs-spi.h.

#define S3C2410_SPPIN_RESERVED   (1 << 1)

Definition at line 41 of file regs-spi.h.

#define S3C2410_SPPRE   (0x0C)

Definition at line 44 of file regs-spi.h.

#define S3C2410_SPRDAT   (0x14)

Definition at line 46 of file regs-spi.h.

#define S3C2410_SPSTA   (0x04)

Definition at line 31 of file regs-spi.h.

#define S3C2410_SPSTA_DCOL   (1 << 2) /* Data Collision Error */

Definition at line 33 of file regs-spi.h.

#define S3C2410_SPSTA_MULD   (1 << 1) /* Multi Master Error */

Definition at line 34 of file regs-spi.h.

#define S3C2410_SPSTA_READY   (1 << 0) /* Data Tx/Rx ready */

Definition at line 35 of file regs-spi.h.

#define S3C2410_SPTDAT   (0x10)

Definition at line 45 of file regs-spi.h.

#define S3C2412_SPI1   (0x100)

Definition at line 16 of file regs-spi.h.

#define S3C2412_SPSTA_READY_ORG   (1 << 3)

Definition at line 36 of file regs-spi.h.