at91rm9200_sdramc.h File Reference

Go to the source code of this file.

Macros
#define	AT91RM9200_SDRAMC_MR   0x90 /* Mode Register */
#define	AT91RM9200_SDRAMC_MODE   (0xf << 0) /* Command Mode */
#define	AT91RM9200_SDRAMC_MODE_NORMAL   (0 << 0)
#define	AT91RM9200_SDRAMC_MODE_NOP   (1 << 0)
#define	AT91RM9200_SDRAMC_MODE_PRECHARGE   (2 << 0)
#define	AT91RM9200_SDRAMC_MODE_LMR   (3 << 0)
#define	AT91RM9200_SDRAMC_MODE_REFRESH   (4 << 0)
#define	AT91RM9200_SDRAMC_DBW   (1 << 4) /* Data Bus Width */
#define	AT91RM9200_SDRAMC_DBW_32   (0 << 4)
#define	AT91RM9200_SDRAMC_DBW_16   (1 << 4)
#define	AT91RM9200_SDRAMC_TR   0x94 /* Refresh Timer Register */
#define	AT91RM9200_SDRAMC_COUNT   (0xfff << 0) /* Refresh Timer Count */
#define	AT91RM9200_SDRAMC_CR   0x98 /* Configuration Register */
#define	AT91RM9200_SDRAMC_NC   (3 << 0) /* Number of Column Bits */
#define	AT91RM9200_SDRAMC_NC_8   (0 << 0)
#define	AT91RM9200_SDRAMC_NC_9   (1 << 0)
#define	AT91RM9200_SDRAMC_NC_10   (2 << 0)
#define	AT91RM9200_SDRAMC_NC_11   (3 << 0)
#define	AT91RM9200_SDRAMC_NR   (3 << 2) /* Number of Row Bits */
#define	AT91RM9200_SDRAMC_NR_11   (0 << 2)
#define	AT91RM9200_SDRAMC_NR_12   (1 << 2)
#define	AT91RM9200_SDRAMC_NR_13   (2 << 2)
#define	AT91RM9200_SDRAMC_NB   (1 << 4) /* Number of Banks */
#define	AT91RM9200_SDRAMC_NB_2   (0 << 4)
#define	AT91RM9200_SDRAMC_NB_4   (1 << 4)
#define	AT91RM9200_SDRAMC_CAS   (3 << 5) /* CAS Latency */
#define	AT91RM9200_SDRAMC_CAS_2   (2 << 5)
#define	AT91RM9200_SDRAMC_TWR   (0xf << 7) /* Write Recovery Delay */
#define	AT91RM9200_SDRAMC_TRC   (0xf << 11) /* Row Cycle Delay */
#define	AT91RM9200_SDRAMC_TRP   (0xf << 15) /* Row Precharge Delay */
#define	AT91RM9200_SDRAMC_TRCD   (0xf << 19) /* Row to Column Delay */
#define	AT91RM9200_SDRAMC_TRAS   (0xf << 23) /* Active to Precharge Delay */
#define	AT91RM9200_SDRAMC_TXSR   (0xf << 27) /* Exit Self Refresh to Active Delay */
#define	AT91RM9200_SDRAMC_SRR   0x9c /* Self Refresh Register */
#define	AT91RM9200_SDRAMC_LPR   0xa0 /* Low Power Register */
#define	AT91RM9200_SDRAMC_IER   0xa4 /* Interrupt Enable Register */
#define	AT91RM9200_SDRAMC_IDR   0xa8 /* Interrupt Disable Register */
#define	AT91RM9200_SDRAMC_IMR   0xac /* Interrupt Mask Register */
#define	AT91RM9200_SDRAMC_ISR   0xb0 /* Interrupt Status Register */

Macro Definition Documentation

#define AT91RM9200_SDRAMC_CAS   (3 << 5) /* CAS Latency */

Definition at line 47 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_CAS_2   (2 << 5)

Definition at line 48 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_COUNT   (0xfff << 0) /* Refresh Timer Count */

Definition at line 32 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_CR   0x98 /* Configuration Register */

Definition at line 34 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_DBW   (1 << 4) /* Data Bus Width */

Definition at line 27 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_DBW_16   (1 << 4)

Definition at line 29 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_DBW_32   (0 << 4)

Definition at line 28 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_IDR   0xa8 /* Interrupt Disable Register */

Definition at line 59 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_IER   0xa4 /* Interrupt Enable Register */

Definition at line 58 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_IMR   0xac /* Interrupt Mask Register */

Definition at line 60 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_ISR   0xb0 /* Interrupt Status Register */

Definition at line 61 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_LPR   0xa0 /* Low Power Register */

Definition at line 57 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_MODE   (0xf << 0) /* Command Mode */

Definition at line 21 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_MODE_LMR   (3 << 0)

Definition at line 25 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_MODE_NOP   (1 << 0)

Definition at line 23 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_MODE_NORMAL   (0 << 0)

Definition at line 22 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_MODE_PRECHARGE   (2 << 0)

Definition at line 24 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_MODE_REFRESH   (4 << 0)

Definition at line 26 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_MR   0x90 /* Mode Register */

Definition at line 20 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_NB   (1 << 4) /* Number of Banks */

Definition at line 44 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_NB_2   (0 << 4)

Definition at line 45 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_NB_4   (1 << 4)

Definition at line 46 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_NC   (3 << 0) /* Number of Column Bits */

Definition at line 35 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_NC_10   (2 << 0)

Definition at line 38 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_NC_11   (3 << 0)

Definition at line 39 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_NC_8   (0 << 0)

Definition at line 36 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_NC_9   (1 << 0)

Definition at line 37 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_NR   (3 << 2) /* Number of Row Bits */

Definition at line 40 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_NR_11   (0 << 2)

Definition at line 41 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_NR_12   (1 << 2)

Definition at line 42 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_NR_13   (2 << 2)

Definition at line 43 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_SRR   0x9c /* Self Refresh Register */

Definition at line 56 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_TR   0x94 /* Refresh Timer Register */

Definition at line 31 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_TRAS   (0xf << 23) /* Active to Precharge Delay */

Definition at line 53 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_TRC   (0xf << 11) /* Row Cycle Delay */

Definition at line 50 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_TRCD   (0xf << 19) /* Row to Column Delay */

Definition at line 52 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_TRP   (0xf << 15) /* Row Precharge Delay */

Definition at line 51 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_TWR   (0xf << 7) /* Write Recovery Delay */

Definition at line 49 of file at91rm9200_sdramc.h.

#define AT91RM9200_SDRAMC_TXSR   (0xf << 27) /* Exit Self Refresh to Active Delay */

Definition at line 54 of file at91rm9200_sdramc.h.